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Merge branch 'master' into new-parallel-parsing
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@mxz297
mxz297 committed Oct 21, 2018
2 parents b89bee2 + 1d7826a commit 46f62dd
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Showing 62 changed files with 3,211 additions and 1,113 deletions.
60 changes: 57 additions & 3 deletions common/src/arch-aarch64.h
View file
Expand Up @@ -56,7 +56,61 @@ namespace NS_aarch64 {
//#define UNCOND_BR_REG (0xd6000000)

#define BREAK_POINT_INSN 0xd4200000
#define ABS(x) ((x) > 0 ? x : -x)

#define BOp 0x05
#define BCondOp 0x2A
#define BRegOp 0xD61F
#define NOOP 0xD503201F

#define ADDShiftOp 0x2B
#define ADDImmOp 0x11
#define SUBShiftOp 0x6B
#define SUBImmOp 0x51
#define MULOp 0xD8
#define SDIVOp 0xD6

#define ORRShiftOp 0x2A
#define ANDShiftOp 0x0A
#define EORShiftOp 0x4A

#define STRImmOp 0x1C0
#define LDRImmOp 0x1C2
#define STRFPImmOp 0x1E0
#define LDRFPImmOp 0x1E2
#define STRImmUIOp 0xE4
#define LDRImmUIOp 0xE5
#define LDRSWImmUIOp 0xE6

#define MSROp 0xD51
#define MRSOp 0xD53
#define MSROp 0xD51
#define MOVSPOp 0x44000

#define MIN_IMM8 (-128)
#define MAX_IMM8 (127)
#define MIN_IMM16 (-32768)
#define MAX_IMM16 (32767)
#define MIN_IMM32 (-2147483647 - 1)
#define MAX_IMM32 (2147483647)
#define MAX_IMM48 ((long)(-1 >> 17))
#define MIN_IMM48 ((long)(~MAX_IMM48))
#define MAX_IMM52 ((long)(1 << 52))
#define MIN_IMM52 ((long)(~MAX_IMM52))

//Would probably want to use the register category as well (FPR/SPR/GPR), but for the uses of these macros, this should suffice
#define SPR_LR (((Dyninst::aarch64::x29).val()) & 0x1F)
#define SPR_NZCV (((Dyninst::aarch64::pstate).val()) & 0x1F)
#define SPR_FPCR (((Dyninst::aarch64::fpcr).val()) & 0x1F)
#define SPR_FPSR (((Dyninst::aarch64::fpsr).val()) & 0x1F)

#define INSN_SET(I, s, e, v) ((I).setBits(s, e - s + 1, (v)))

#define INSN_GET_ISCALL(I) ((unsigned int) ((I).asInt() & 0x80000000))
#define INSN_GET_CBRANCH_OFFSET(I) ((unsigned int) (((I).asInt() >> 5) & 0x7ffff))

#define MAX_BRANCH_OFFSET 0x07ffffff // 128MB Used for B
#define MAX_CBRANCH_OFFSET 0x000fffff // 1MB Used for B.cond, CBZ and CBNZ
#define MAX_TBRANCH_OFFSET 0x0007ffff // 32KB Used for TBZ and TBNZ

#define CHECK_INST(isInst) \
!((insn_.raw&isInst##_MASK)^isInst)
Expand Down Expand Up @@ -92,9 +146,9 @@ class COND_BR_t {
static insn_mask CB_MASK = 0x7e000000; // comp&B
static insn_mask TB_MASK = 0x7e000000; // test&B

static insn_mask BR = 0x54000000; // Conditional B
static insn_mask CB = 0x34000000; // Compare & B
static insn_mask TB = 0x36000000; // Test & B
static insn_mask BR = 0x54000000; // Conditional B

static insn_mask CB_OFFSET_MASK = 0x07fffff0;
static insn_mask TB_OFFSET_MASK = 0x0007fff0;
Expand Down Expand Up @@ -148,7 +202,7 @@ class COMMON_EXPORT instruction {
void setBits(unsigned int pos, unsigned int len, unsigned int value) {
unsigned int mask;

mask = ~(~0u << len);
mask = ~((unsigned int)(~0) << len);
value = value & mask;

mask = ~(mask << pos);
Expand Down
3 changes: 2 additions & 1 deletion common/src/arch-power.h
View file
Expand Up @@ -512,6 +512,8 @@ typedef unsigned codeBufIndex_t;
#define ANDxop 28 /* and */
#define ORop 31 /* or */
#define ORxop 444 /* or */
#define XORop 31
#define XORxop 316

// -- Other extended op codes for X, XFX, & XO when op is 31
#define EXTop 31
Expand Down Expand Up @@ -557,7 +559,6 @@ typedef unsigned codeBufIndex_t;
#define DCBTxop 278
#define EQVxop 284
#define TLBIxop 306
#define XORxop 316
#define DIVxop 331
#define ABSxop 360
#define ORCxop 412
Expand Down
12 changes: 8 additions & 4 deletions dataflowAPI/rose/semantics/DispatcherARM64.C
View file
Expand Up @@ -486,8 +486,10 @@ namespace rose {
ops->or_(ops->and_(base, ops->number_(64, 0xfffffffffffff000)),
d->Zeros(12));
}

d->write(args[0], ops->add(base, d->read(args[1])));
// args[1] is in the form of PC + offset
// we do not want PC to appear twice, so we extract the offset
SgAsmBinaryExpression * addOp = dynamic_cast<SgAsmBinaryExpression*>(args[1]);
d->write(args[0], ops->add(base, d->read(addOp->get_rhs())));
}
};

Expand All @@ -501,8 +503,10 @@ namespace rose {
ops->or_(ops->and_(base, ops->number_(64, 0xfffffffffffff000)),
d->Zeros(12));
}

d->write(args[0], ops->add(base, d->read(args[1])));
// args[1] is in the form of PC + offset
// we do not want PC to appear twice, so we extract the offset
SgAsmBinaryExpression * addOp = dynamic_cast<SgAsmBinaryExpression*>(args[1]);
d->write(args[0], ops->add(base, d->read(addOp->get_rhs())));
}
};

Expand Down
116 changes: 103 additions & 13 deletions dataflowAPI/src/ABI.C
View file
Expand Up @@ -87,8 +87,8 @@ ABI* ABI::getABI(int addr_width){
//#warning "This is not verified yet!"
#if defined(arch_aarch64)
globalABI64_->addr_width = 8;
globalABI_->index = &machRegIndex_ppc();
globalABI64_->index = &machRegIndex_ppc();
globalABI_->index = &machRegIndex_aarch64();
globalABI64_->index = &machRegIndex_aarch64();
#endif

initialize32();
Expand Down Expand Up @@ -217,11 +217,9 @@ void ABI::initialize32(){
(*callRead_)[machRegIndex_x86()[x86::ebx]] = true;

// TODO: Fix this for platform-specific calling conventions

// Assume calls write flags

callWritten_ = new bitArray(machRegIndex_x86().size());
*callWritten_ = *callRead_;

// Assume calls write flags
(*callWritten_)[machRegIndex_x86()[x86::of]] = true;
(*callWritten_)[machRegIndex_x86()[x86::sf]] = true;
(*callWritten_)[machRegIndex_x86()[x86::zf]] = true;
Expand All @@ -234,12 +232,11 @@ void ABI::initialize32(){
(*callWritten_)[machRegIndex_x86()[x86::nt_]] = true;
(*callWritten_)[machRegIndex_x86()[x86::rf]] = true;



// And eax...
// And scratch registers: eax, ecx, edx
(*callWritten_)[machRegIndex_x86()[x86::eax]] = true;


(*callWritten_)[machRegIndex_x86()[x86::ecx]] = true;
(*callWritten_)[machRegIndex_x86()[x86::edx]] = true;

// And assume a syscall reads or writes _everything_
syscallRead_ = new bitArray(machRegIndex_x86().size());
syscallRead_->set();
Expand Down Expand Up @@ -557,10 +554,103 @@ void ABI::initialize64(){
//#warning "This is not verified!"
#if defined(arch_aarch64)
void ABI::initialize32(){
assert(0);
return;
}

void ABI::initialize64(){
assert(0);
RegisterMap aarch64Map = machRegIndex_aarch64();
int sz = aarch64Map.size();

returnRegs64_ = getBitArray(sz);
returnRegs64_[aarch64Map[aarch64::x0]] = true;
returnRegs64_[aarch64Map[aarch64::q0]] = true;

returnRead64_ = getBitArray(sz);
returnRead64_[aarch64Map[aarch64::x0]] = true;
returnRead64_[aarch64Map[aarch64::q0]] = true;
//Callee-saved registers
//First, GPRs...
returnRead64_[aarch64Map[aarch64::x19]] = true;
returnRead64_[aarch64Map[aarch64::x20]] = true;
returnRead64_[aarch64Map[aarch64::x21]] = true;
returnRead64_[aarch64Map[aarch64::x22]] = true;
returnRead64_[aarch64Map[aarch64::x23]] = true;
returnRead64_[aarch64Map[aarch64::x24]] = true;
returnRead64_[aarch64Map[aarch64::x25]] = true;
returnRead64_[aarch64Map[aarch64::x26]] = true;
returnRead64_[aarch64Map[aarch64::x27]] = true;
returnRead64_[aarch64Map[aarch64::x28]] = true;
returnRead64_[aarch64Map[aarch64::sp]] = true;
//Now, SIMD regs...
returnRead64_[aarch64Map[aarch64::q8]] = true;
returnRead64_[aarch64Map[aarch64::q9]] = true;
returnRead64_[aarch64Map[aarch64::q10]] = true;
returnRead64_[aarch64Map[aarch64::q11]] = true;
returnRead64_[aarch64Map[aarch64::q12]] = true;
returnRead64_[aarch64Map[aarch64::q13]] = true;
returnRead64_[aarch64Map[aarch64::q14]] = true;
returnRead64_[aarch64Map[aarch64::q15]] = true;

callParam64_ = getBitArray(sz);
callParam64_[aarch64Map[aarch64::x0]] = true;
callParam64_[aarch64Map[aarch64::x1]] = true;
callParam64_[aarch64Map[aarch64::x2]] = true;
callParam64_[aarch64Map[aarch64::x3]] = true;
callParam64_[aarch64Map[aarch64::x4]] = true;
callParam64_[aarch64Map[aarch64::x5]] = true;
callParam64_[aarch64Map[aarch64::x6]] = true;
callParam64_[aarch64Map[aarch64::x7]] = true;

callRead64_ = getBitArray(sz);
//First, GPRs...
callRead64_[aarch64Map[aarch64::x0]] = true;
callRead64_[aarch64Map[aarch64::x1]] = true;
callRead64_[aarch64Map[aarch64::x2]] = true;
callRead64_[aarch64Map[aarch64::x3]] = true;
callRead64_[aarch64Map[aarch64::x4]] = true;
callRead64_[aarch64Map[aarch64::x5]] = true;
callRead64_[aarch64Map[aarch64::x6]] = true;
callRead64_[aarch64Map[aarch64::x7]] = true;
//Now, SIMD regs...
callRead64_[aarch64Map[aarch64::q0]] = true;
callRead64_[aarch64Map[aarch64::q1]] = true;
callRead64_[aarch64Map[aarch64::q2]] = true;
callRead64_[aarch64Map[aarch64::q3]] = true;
callRead64_[aarch64Map[aarch64::q4]] = true;
callRead64_[aarch64Map[aarch64::q5]] = true;
callRead64_[aarch64Map[aarch64::q6]] = true;
callRead64_[aarch64Map[aarch64::q7]] = true;

callWritten64_ = callRead64_;
//First, GPRs...
callWritten64_[aarch64Map[aarch64::x9]] = true;
callWritten64_[aarch64Map[aarch64::x10]] = true;
callWritten64_[aarch64Map[aarch64::x11]] = true;
callWritten64_[aarch64Map[aarch64::x12]] = true;
callWritten64_[aarch64Map[aarch64::x13]] = true;
callWritten64_[aarch64Map[aarch64::x14]] = true;
callWritten64_[aarch64Map[aarch64::x15]] = true;
//Now, SIMD regs...
callWritten64_[aarch64Map[aarch64::q16]] = true;
callWritten64_[aarch64Map[aarch64::q17]] = true;
callWritten64_[aarch64Map[aarch64::q18]] = true;
callWritten64_[aarch64Map[aarch64::q19]] = true;
callWritten64_[aarch64Map[aarch64::q20]] = true;
callWritten64_[aarch64Map[aarch64::q21]] = true;
callWritten64_[aarch64Map[aarch64::q22]] = true;
callWritten64_[aarch64Map[aarch64::q23]] = true;
callWritten64_[aarch64Map[aarch64::q24]] = true;
callWritten64_[aarch64Map[aarch64::q25]] = true;
callWritten64_[aarch64Map[aarch64::q26]] = true;
callWritten64_[aarch64Map[aarch64::q27]] = true;
callWritten64_[aarch64Map[aarch64::q28]] = true;
callWritten64_[aarch64Map[aarch64::q29]] = true;
callWritten64_[aarch64Map[aarch64::q30]] = true;
callWritten64_[aarch64Map[aarch64::q31]] = true;

syscallRead64_ = getBitArray(sz).set();
syscallWritten64_ = getBitArray(sz).set();

allRegs64_ = getBitArray(sz).set();
}
#endif

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