Append "2" to the mnemonic of SIMD instructions that operate on the

upper 64-bits of the registers holding narrower elements. Also fixes issues #269 and #255.
dyninst · Dec 22, 2016 · 4ec677a · 4ec677a
1 parent c3b1082
commit 4ec677a
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diff --git a/instructionAPI/src/InstructionDecoder-aarch64.C b/instructionAPI/src/InstructionDecoder-aarch64.C
@@ -2539,6 +2539,33 @@ Expression::Ptr InstructionDecoder_aarch64::makeMemRefExPair2(){
 	    if(skipRm)
 		cond = ((cond % 2) == 0) ? (cond + 1) : (cond - 1);
         }
+
+	void InstructionDecoder_aarch64::modify_mnemonic_simd_upperhalf_insns() {
+	    if(field<30, 30>(insn) != 1)
+		return;
+
+	    string cur_mnemonic = insn_in_progress->getOperation().mnemonic;
+	    bool add2 = false;
+
+	    if(IS_INSN_SIMD_3DIFF(insn) || IS_INSN_SCALAR_3DIFF(insn))
+		add2 = true;
+	    else if(IS_INSN_SCALAR_2REG_MISC(insn) || IS_INSN_SIMD_2REG_MISC(insn)) {
+		int checkval = (field<12, 16>(insn) >> 2) & 0x7;
+		if(checkval == 0x4 || checkval == 0x5)
+		    add2 = true;
+	    } else if(IS_INSN_SIMD_SHIFT_IMM(insn) || IS_INSN_SCALAR_SHIFT_IMM(insn)) {
+		int checkval = (field<11, 15>(insn) >> 2) & 0x7;
+		if(checkval == 0x4 || (IS_INSN_SIMD_SHIFT_IMM(insn) && checkval == 0x5))
+		    add2 = true;
+	    } else if(IS_INSN_SIMD_VEC_INDEX(insn) || IS_INSN_SCALAR_INDEX(insn)) {
+		int checkval = field<12, 15>(insn) & 0x3;
+		if((checkval >> 1) == 0x1 || (IS_INSN_SCALAR_INDEX(insn) && (checkval & 0x1) == 0x1))
+		    add2 = true;
+	    }
+
+	    if(add2)
+		insn_in_progress->getOperation().mnemonic = cur_mnemonic + "2";
+	}
 
         template<unsigned int endBit, unsigned int startBit>
         void InstructionDecoder_aarch64::OPRimm() {
@@ -3019,6 +3046,8 @@ Expression::Ptr InstructionDecoder_aarch64::makeMemRefExPair2(){
             insn_in_progress = makeInstruction(insn_table_entry->op, insn_table_entry->mnemonic, 4,
                                                reinterpret_cast<unsigned char *>(&insn));
 
+	    modify_mnemonic_simd_upperhalf_insns();
+
             if (IS_INSN_BRANCHING(insn)) {
                 decodeOperands(insn_in_progress);
             }

diff --git a/instructionAPI/src/InstructionDecoder-aarch64.h b/instructionAPI/src/InstructionDecoder-aarch64.h
@@ -123,6 +123,7 @@ namespace Dyninst {
 #define    IS_INSN_BRANCHING(I)            (IS_INSN_B_COND(I) || IS_INSN_B_UNCOND(I) || IS_INSN_B_UNCOND_REG(I) || IS_INSN_B_TEST(I)|| IS_INSN_B_COMPARE(I))
 
 #define IS_INSN_SIMD_3DIFF(I)           (field<31, 31>(I) == 0x0 && field<24, 28>(I) == 0xe && field<21, 21>(I) == 0x1 && field<10, 11>(I) == 0x0)
+#define IS_INSN_SIMD_2REG_MISC(I)	(field<31, 31>(I) == 0x0 && field<24, 28>(I) == 0xe && field<17, 21>(I) == 0x10 && field<10, 11>(I) == 0x2)	    
 #define IS_INSN_SIMD_ACROSS(I)          (field<31, 31>(I) == 0x0 && field<24, 28>(I) == 0xe && field<17, 21>(I) == 0x18 && field<10, 11>(I) == 0x2)
 #define IS_INSN_SIMD_COPY(I)            (field<31, 31>(I) == 0x0 && field<21, 28>(I) == 0x70 && field<15,15>(I) == 0x0 && field<10, 10>(I) == 0x1)
 #define IS_INSN_SIMD_VEC_INDEX(I)       (field<31, 31>(I) == 0x0 && field<24, 28>(I) == 0xf && field<10, 10>(I) == 0x0)
@@ -269,6 +270,7 @@ namespace Dyninst {
 
             bool fix_bitfieldinsn_alias(int, int);
 	    void fix_condinsn_alias_and_cond(int &);
+	    void modify_mnemonic_simd_upperhalf_insns();
 
             MachRegister makeAarch64RegID(MachRegister, unsigned int);