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Use Dyninst::Address in codegen-aarch64
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@hainest
hainest committed Nov 5, 2023
1 parent 481899f commit 593ebb6
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Showing 2 changed files with 38 additions and 37 deletions.
38 changes: 19 additions & 19 deletions dyninstAPI/src/codegen-aarch64.C
View file
Expand Up @@ -113,7 +113,7 @@ void insnCodeGen::generateBranch(codeGen &gen, long disp, bool link) {
insnCodeGen::generate(gen, insn);
}

void insnCodeGen::generateBranch(codeGen &gen, Address from, Address to, bool link) {
void insnCodeGen::generateBranch(codeGen &gen, Dyninst::Address from, Dyninst::Address to, bool link) {
long disp = (to - from);

if (labs(disp) > MAX_BRANCH_OFFSET) {
Expand All @@ -122,13 +122,13 @@ void insnCodeGen::generateBranch(codeGen &gen, Address from, Address to, bool li
generateBranch(gen, disp, link);
}

void insnCodeGen::generateCall(codeGen &gen, Address from, Address to) {
void insnCodeGen::generateCall(codeGen &gen, Dyninst::Address from, Dyninst::Address to) {
generateBranch(gen, from, to, true);
}

void insnCodeGen::generateLongBranch(codeGen &gen,
Address from,
Address to,
Dyninst::Address from,
Dyninst::Address to,
bool isCall)
{
auto generateBReg = [&isCall, &gen](Register s) -> void
Expand Down Expand Up @@ -185,7 +185,7 @@ void insnCodeGen::generateLongBranch(codeGen &gen,
generateBReg(scratch);
}

void insnCodeGen::generateBranchViaTrap(codeGen &gen, Address from, Address to, bool isCall) {
void insnCodeGen::generateBranchViaTrap(codeGen &gen, Dyninst::Address from, Dyninst::Address to, bool isCall) {
long disp = to - from;
if (labs(disp) <= MAX_BRANCH_OFFSET) {
// We shouldn't be here, since this is an internal-called-only func.
Expand All @@ -210,7 +210,7 @@ void insnCodeGen::generateBranchViaTrap(codeGen &gen, Address from, Address to,
}
}

void insnCodeGen::generateConditionalBranch(codeGen& gen, Address to, unsigned opcode, bool s)
void insnCodeGen::generateConditionalBranch(codeGen& gen, Dyninst::Address to, unsigned opcode, bool s)
{
instruction insn;
insn.clear();
Expand Down Expand Up @@ -481,7 +481,7 @@ Register insnCodeGen::moveValueToReg(codeGen &gen, long int val, std::vector<Reg
assert(0);
}

loadImmIntoReg(gen, scratchReg, static_cast<Address>(val));
loadImmIntoReg(gen, scratchReg, static_cast<Dyninst::Address>(val));

return scratchReg;
}
Expand Down Expand Up @@ -651,8 +651,8 @@ assert(0);

bool insnCodeGen::generateMem(codeGen &,
instruction&,
Address,
Address,
Dyninst::Address,
Dyninst::Address,
Register,
Register) {
assert(0);
Expand All @@ -673,7 +673,7 @@ assert(0);
//#warning "This function is not implemented yet!"
}

bool insnCodeGen::modifyJump(Address target,
bool insnCodeGen::modifyJump(Dyninst::Address target,
NS_aarch64::instruction &insn,
codeGen &gen) {
long disp = target - gen.currAddr();
Expand Down Expand Up @@ -704,7 +704,7 @@ bool insnCodeGen::modifyJump(Address target,
* bit-twiddling functions can then be defined if necessary in the codegen-* files
* and called as necessary by the common, refactored logic.
*/
bool insnCodeGen::modifyJcc(Address target,
bool insnCodeGen::modifyJcc(Dyninst::Address target,
NS_aarch64::instruction &insn,
codeGen &gen) {
long disp = target - gen.currAddr();
Expand All @@ -713,7 +713,7 @@ bool insnCodeGen::modifyJcc(Address target,
if(labs(disp) > MAX_CBRANCH_OFFSET ||
(isTB && labs(disp) > MAX_TBRANCH_OFFSET))
{
Address origFrom = gen.currAddr();
Dyninst::Address origFrom = gen.currAddr();

/*
* A conditional branch of the form:
Expand Down Expand Up @@ -754,7 +754,7 @@ bool insnCodeGen::modifyJcc(Address target,
* bytes (8 actually, but I'm not hardcoding this) ahead of the original 'from' address.
* So adjust it accordingly.*/
codeBufIndex_t curIdx = gen.getIndex();
Address newFrom = origFrom + (unsigned)(curIdx - startIdx);
Dyninst::Address newFrom = origFrom + (unsigned)(curIdx - startIdx);
insnCodeGen::generateBranch(gen, newFrom, target);
}
else
Expand All @@ -773,7 +773,7 @@ bool insnCodeGen::modifyJcc(Address target,
return true;
}

bool insnCodeGen::modifyCall(Address target,
bool insnCodeGen::modifyCall(Dyninst::Address target,
NS_aarch64::instruction &insn,
codeGen &gen) {
if (insn.isUncondBranch())
Expand All @@ -782,7 +782,7 @@ bool insnCodeGen::modifyCall(Address target,
return modifyJcc(target, insn, gen);
}

bool insnCodeGen::modifyData(Address target,
bool insnCodeGen::modifyData(Dyninst::Address target,
NS_aarch64::instruction &insn,
codeGen &gen)
{
Expand All @@ -793,14 +793,14 @@ bool insnCodeGen::modifyData(Address target,
isneg = true;

if (((raw >> 24) & 0x1F) == 0x10) {
Address offset;
Dyninst::Address offset;
if((static_cast<uint32_t>(raw) >> 31) & 0x1) {
target &= 0xFFFFF000;
Address cur = gen.currAddr() & 0xFFFFF000;
Dyninst::Address cur = gen.currAddr() & 0xFFFFF000;
offset = isneg ? (cur - target) : (target - cur);
offset >>= 12;
} else {
Address cur = gen.currAddr();
Dyninst::Address cur = gen.currAddr();
offset = isneg ? (cur - target) : (target - cur);
}
signed long imm = isneg ? -((signed long)offset) : offset;
Expand Down Expand Up @@ -836,7 +836,7 @@ bool insnCodeGen::modifyData(Address target,

}
} else if (((raw >> 24) & 0x3F) == 0x18 || ((raw >> 24) & 0x3F) == 0x1C) {
Address offset = !isneg ? (target - gen.currAddr()) : (gen.currAddr() - target);
Dyninst::Address offset = !isneg ? (target - gen.currAddr()) : (gen.currAddr() - target);
//If offset is within +/- 1 MB, modify the instruction (LDR/LDRSW) with the new offset
if (offset <= (1 << 20)) {
instruction newInsn(insn);
Expand Down
37 changes: 19 additions & 18 deletions dyninstAPI/src/codegen-aarch64.h
View file
Expand Up @@ -32,6 +32,7 @@
#define _CODEGEN_AARCH64_H

#include <vector>
#include "dyntypes.h"

class AddressSpace;

Expand Down Expand Up @@ -81,27 +82,27 @@ class insnCodeGen {
bool link = false);

static void generateBranch(codeGen &gen,
Address from,
Address to,
Dyninst::Address from,
Dyninst::Address to,
bool link = false);

static void generateCall(codeGen &gen,
Address from,
Address to);
Dyninst::Address from,
Dyninst::Address to);

static void generateLongBranch(codeGen &gen,
Address from,
Address to,
Dyninst::Address from,
Dyninst::Address to,
bool isCall);

// Using the process trap mapping for a branch
static void generateBranchViaTrap(codeGen &gen,
Address from,
Address to,
Dyninst::Address from,
Dyninst::Address to,
bool isCall);

// Generate conditional branch
static void generateConditionalBranch(codeGen& gen, Address to, unsigned opcode, bool s);
static void generateConditionalBranch(codeGen& gen, Dyninst::Address to, unsigned opcode, bool s);

// LDR/STR (immediate)
// immd in the range -256 to 255
Expand All @@ -111,7 +112,7 @@ class insnCodeGen {
static void generateMemAccessFP(codeGen &gen, LoadStore accType, Register rt,
Register rn, int immd, int size, bool is128bit, IndexMode im=Offset);

static inline void loadImmIntoReg(codeGen &gen, Register rt, Address value)
static inline void loadImmIntoReg(codeGen &gen, Register rt, Dyninst::Address value)
{
insnCodeGen::generateMove(gen, (value & 0xFFFF), 0, rt, MovOp_MOVZ);
if(value > 0xFFFF)
Expand Down Expand Up @@ -166,8 +167,8 @@ class insnCodeGen {

static bool generateMem(codeGen &gen,
instruction &insn,
Address origAddr,
Address newAddr,
Dyninst::Address origAddr,
Dyninst::Address newAddr,
Register newLoadReg,
Register newStoreReg);

Expand Down Expand Up @@ -206,8 +207,8 @@ class insnCodeGen {
static bool generate(codeGen &gen,
instruction &insn,
AddressSpace *proc,
Address origAddr,
Address newAddr,
Dyninst::Address origAddr,
Dyninst::Address newAddr,
patchTarget *fallthroughOverride = NULL,
patchTarget *targetOverride = NULL);

Expand All @@ -222,19 +223,19 @@ class insnCodeGen {

static void generateNOOP(codeGen &gen, unsigned size = 4);

static bool modifyJump(Address target,
static bool modifyJump(Dyninst::Address target,
NS_aarch64::instruction &insn,
codeGen &gen);

static bool modifyJcc(Address target,
static bool modifyJcc(Dyninst::Address target,
NS_aarch64::instruction &insn,
codeGen &gen);

static bool modifyCall(Address target,
static bool modifyCall(Dyninst::Address target,
NS_aarch64::instruction &insn,
codeGen &gen);

static bool modifyData(Address target,
static bool modifyData(Dyninst::Address target,
NS_aarch64::instruction &insn,
codeGen &gen);
};
Expand Down

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