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Remove deleted x86 RegisterDictionary functions (#1632)
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These were commented out by 5582278 in 2016.
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@hainest
hainest committed Nov 24, 2023
1 parent 30f08e7 commit 6382220
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336 changes: 0 additions & 336 deletions dataflowAPI/rose/semantics/Registers.C
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Expand Up @@ -245,342 +245,6 @@ RegisterDictionary::print(std::ostream &o) const {
}
}

/** Intel 8086 registers.
*
* The Intel 8086 has fourteen 16-bit registers. Four of them (AX, BX, CX, DX) are general registers (although each may have
* an additional purpose; for example only CX can be used as a counter with the loop instruction). Each can be accessed as two
* separate bytes (thus BX's high byte can be accessed as BH and low byte as BL). Four segment registers (CS, DS, SS and ES)
* are used to form a memory address. There are two pointer registers. SP points to the bottom of the stack and BP which is
* used to point at some other place in the stack or the memory(Offset). Two registers (SI and DI) are for array
* indexing. The FLAGS register contains flags such as carry flag, overflow flag and zero flag. Finally, the instruction
* pointer (IP) points to the next instruction that will be fetched from memory and then executed. */
//const RegisterDictionary *
//RegisterDictionary::dictionary_i8086() {
// static RegisterDictionary *regs = NULL;
// if (!regs) {
// regs = new RegisterDictionary("i8086");
//
// /* 16-bit general purpose registers. Each has three names depending on which bytes are reference. */
// regs->insert("al", x86_regclass_gpr, x86_gpr_ax, 0, 8);
// regs->insert("ah", x86_regclass_gpr, x86_gpr_ax, 8, 8);
// regs->insert("ax", x86_regclass_gpr, x86_gpr_ax, 0, 16);
//
// regs->insert("bl", x86_regclass_gpr, x86_gpr_bx, 0, 8);
// regs->insert("bh", x86_regclass_gpr, x86_gpr_bx, 8, 8);
// regs->insert("bx", x86_regclass_gpr, x86_gpr_bx, 0, 16);
//
// regs->insert("cl", x86_regclass_gpr, x86_gpr_cx, 0, 8);
// regs->insert("ch", x86_regclass_gpr, x86_gpr_cx, 8, 8);
// regs->insert("cx", x86_regclass_gpr, x86_gpr_cx, 0, 16);
//
// regs->insert("dl", x86_regclass_gpr, x86_gpr_dx, 0, 8);
// regs->insert("dh", x86_regclass_gpr, x86_gpr_dx, 8, 8);
// regs->insert("dx", x86_regclass_gpr, x86_gpr_dx, 0, 16);
//
// /* 16-bit segment registers */
// regs->insert("cs", x86_regclass_segment, x86_segreg_cs, 0, 16);
// regs->insert("ds", x86_regclass_segment, x86_segreg_ds, 0, 16);
// regs->insert("ss", x86_regclass_segment, x86_segreg_ss, 0, 16);
// regs->insert("es", x86_regclass_segment, x86_segreg_es, 0, 16);
//
// /* 16-bit pointer registers */
// regs->insert("sp", x86_regclass_gpr, x86_gpr_sp, 0, 16); /* stack pointer */
// regs->insert("spl", x86_regclass_gpr, x86_gpr_sp, 0, 8);
//
// regs->insert("bp", x86_regclass_gpr, x86_gpr_bp, 0, 16); /* base pointer */
// regs->insert("bpl", x86_regclass_gpr, x86_gpr_bp, 0, 8);
//
// regs->insert("ip", x86_regclass_ip, 0, 0, 16); /* instruction pointer */
// regs->insert("ipl", x86_regclass_ip, 0, 0, 8);
//
// /* Array indexing registers */
// regs->insert("si", x86_regclass_gpr, x86_gpr_si, 0, 16);
// regs->insert("sil", x86_regclass_gpr, x86_gpr_si, 0, 8);
//
// regs->insert("di", x86_regclass_gpr, x86_gpr_di, 0, 16);
// regs->insert("dil", x86_regclass_gpr, x86_gpr_di, 0, 8);
//
// /* Flags with official names. */
// regs->insert("flags", x86_regclass_flags, x86_flags_status, 0, 16); /* all flags */
// regs->insert("cf", x86_regclass_flags, x86_flags_status, 0, 1); /* carry status flag */
// regs->insert("pf", x86_regclass_flags, x86_flags_status, 2, 1); /* parity status flag */
// regs->insert("af", x86_regclass_flags, x86_flags_status, 4, 1); /* adjust status flag */
// regs->insert("zf", x86_regclass_flags, x86_flags_status, 6, 1); /* zero status flag */
// regs->insert("sf", x86_regclass_flags, x86_flags_status, 7, 1); /* sign status flag */
// regs->insert("tf", x86_regclass_flags, x86_flags_status, 8, 1); /* trap system flag */
// regs->insert("if", x86_regclass_flags, x86_flags_status, 9, 1); /* interrupt enable system flag */
// regs->insert("df", x86_regclass_flags, x86_flags_status, 10, 1); /* direction control flag */
// regs->insert("of", x86_regclass_flags, x86_flags_status, 11, 1); /* overflow status flag */
// regs->insert("nt", x86_regclass_flags, x86_flags_status, 14, 1); /* nested task system flag */
//
// /* Flags without names */
// regs->insert("f1", x86_regclass_flags, x86_flags_status, 1, 1);
// regs->insert("f3", x86_regclass_flags, x86_flags_status, 3, 1);
// regs->insert("f5", x86_regclass_flags, x86_flags_status, 5, 1);
// regs->insert("f12", x86_regclass_flags, x86_flags_status, 12, 1);
// regs->insert("f13", x86_regclass_flags, x86_flags_status, 13, 1);
// regs->insert("f15", x86_regclass_flags, x86_flags_status, 15, 1);
// }
// return regs;
//}
//
///** Intel 8088 registers.
// *
// * Intel 8088 has the same set of registers as Intel 8086. */
//const RegisterDictionary *
//RegisterDictionary::dictionary_i8088()
//{
// static RegisterDictionary *regs = NULL;
// if (!regs) {
// regs = new RegisterDictionary("i8088");
// regs->insert(dictionary_i8086());
// }
// return regs;
//}
//
///** Intel 80286 registers.
// *
// * The 80286 has the same registers as the 8086 but adds two new flags to the "flags" register. */
//const RegisterDictionary *
//RegisterDictionary::dictionary_i286()
//{
// static RegisterDictionary *regs = NULL;
// if (!regs) {
// regs = new RegisterDictionary("i286");
// regs->insert(dictionary_i8086());
// regs->insert("iopl", x86_regclass_flags, x86_flags_status, 12, 2); /* I/O privilege level flag */
// regs->insert("nt", x86_regclass_flags, x86_flags_status, 14, 1); /* nested task system flag */
// }
// return regs;
//}
//
///** Intel 80386 registers.
// *
// * The 80386 has the same registers as the 80286 but extends the general-purpose registers, base registers, index registers,
// * instruction pointer, and flags register to 32 bits. Register names from the 80286 refer to the same offsets and sizes while
// * the full 32 bits are accessed by names prefixed with "e" as in "eax" (the "e" means "extended"). Two new segment registers
// * (FS and GS) were added and all segment registers remain 16 bits. */
//const RegisterDictionary *
//RegisterDictionary::dictionary_i386()
//{
// static RegisterDictionary *regs = NULL;
// if (!regs) {
// regs = new RegisterDictionary("i386");
// regs->insert(dictionary_i286());
//
// /* Additional 32-bit registers */
// regs->insert("eax", x86_regclass_gpr, x86_gpr_ax, 0, 32);
// regs->insert("ebx", x86_regclass_gpr, x86_gpr_bx, 0, 32);
// regs->insert("ecx", x86_regclass_gpr, x86_gpr_cx, 0, 32);
// regs->insert("edx", x86_regclass_gpr, x86_gpr_dx, 0, 32);
// regs->insert("esp", x86_regclass_gpr, x86_gpr_sp, 0, 32);
// regs->insert("ebp", x86_regclass_gpr, x86_gpr_bp, 0, 32);
// regs->insert("eip", x86_regclass_ip, 0, 0, 32);
// regs->insert("esi", x86_regclass_gpr, x86_gpr_si, 0, 32);
// regs->insert("edi", x86_regclass_gpr, x86_gpr_di, 0, 32);
// regs->insert("eflags", x86_regclass_flags, x86_flags_status, 0, 32);
//
// /* Additional 16-bit segment registers */
// regs->insert("fs", x86_regclass_segment, x86_segreg_fs, 0, 16);
// regs->insert("gs", x86_regclass_segment, x86_segreg_gs, 0, 16);
//
// /* Additional flags */
// regs->insert("rf", x86_regclass_flags, x86_flags_status, 16, 1); /* resume system flag */
// regs->insert("vm", x86_regclass_flags, x86_flags_status, 17, 1); /* virtual 8086 mode flag */
//
// /* Additional flag bits that have no official names */
// for (unsigned i=18; i<32; ++i)
// regs->insert("f"+StringUtility::numberToString(i), x86_regclass_flags, x86_flags_status, i, 1);
//
// /* Control registers */
// regs->insert("cr0", x86_regclass_cr, 0, 0, 32);
// regs->insert("cr1", x86_regclass_cr, 1, 0, 32);
// regs->insert("cr2", x86_regclass_cr, 2, 0, 32);
// regs->insert("cr3", x86_regclass_cr, 3, 0, 32);
// regs->insert("cr4", x86_regclass_cr, 4, 0, 32);
//
// /* Debug registers */
// regs->insert("dr0", x86_regclass_dr, 0, 0, 32);
// regs->insert("dr1", x86_regclass_dr, 1, 0, 32);
// regs->insert("dr2", x86_regclass_dr, 2, 0, 32);
// regs->insert("dr3", x86_regclass_dr, 3, 0, 32); /* dr4 and dr5 are reserved */
// regs->insert("dr6", x86_regclass_dr, 6, 0, 32);
// regs->insert("dr7", x86_regclass_dr, 7, 0, 32);
//
// }
// return regs;
//}
//
///** Intel 80386 with 80387 math co-processor. */
//const RegisterDictionary *
//RegisterDictionary::dictionary_i386_387()
//{
// static RegisterDictionary *regs = NULL;
// if (!regs) {
// regs = new RegisterDictionary("i386 w/387");
// regs->insert(dictionary_i386());
//
// // The 387 contains eight floating-point registers that have no names (we call them "st0" through "st7"), and defines
// // expressions of the form "st(n)" to refer to the current nth register from the top of a circular stack. These
// // expressions are implemented usng SgAsmIndexedRegisterExpression IR nodes, which have a base register which is
// // "st0", a stride which increments the minor number, an offset which is the current top-of-stack value, an index
// // which is the value "n" in the expression "st(n)", and a modulus of eight. The current top-of-stack value is held in
// // the three-bit register "fpstatus_top", which normally has a concrete value.
// regs->insert("st0", x86_regclass_st, x86_st_0, 0, 80);
// regs->insert("st1", x86_regclass_st, x86_st_1, 0, 80);
// regs->insert("st2", x86_regclass_st, x86_st_2, 0, 80);
// regs->insert("st3", x86_regclass_st, x86_st_3, 0, 80);
// regs->insert("st4", x86_regclass_st, x86_st_4, 0, 80);
// regs->insert("st5", x86_regclass_st, x86_st_5, 0, 80);
// regs->insert("st6", x86_regclass_st, x86_st_6, 0, 80);
// regs->insert("st7", x86_regclass_st, x86_st_7, 0, 80);
//
// // Floating-point tag registers, two bits per ST register.
// regs->insert("fptag", x86_regclass_flags, x86_flags_fptag, 0, 16); // all tags
// regs->insert("fptag_st0", x86_regclass_flags, x86_flags_fptag, 0, 2); // tag for st0
// regs->insert("fptag_st1", x86_regclass_flags, x86_flags_fptag, 2, 2); // tag for st1
// regs->insert("fptag_st2", x86_regclass_flags, x86_flags_fptag, 4, 2); // tag for st2
// regs->insert("fptag_st3", x86_regclass_flags, x86_flags_fptag, 6, 2); // tag for st3
// regs->insert("fptag_st4", x86_regclass_flags, x86_flags_fptag, 8, 2); // tag for st4
// regs->insert("fptag_st5", x86_regclass_flags, x86_flags_fptag, 10, 2); // tag for st5
// regs->insert("fptag_st6", x86_regclass_flags, x86_flags_fptag, 12, 2); // tag for st6
// regs->insert("fptag_st7", x86_regclass_flags, x86_flags_fptag, 14, 2); // tag for st7
//
// // Floating-point status register
// regs->insert("fpstatus", x86_regclass_flags, x86_flags_fpstatus, 0, 16);
// regs->insert("fpstatus_ie", x86_regclass_flags, x86_flags_fpstatus, 0, 1); // invalid operation
// regs->insert("fpstatus_de", x86_regclass_flags, x86_flags_fpstatus, 1, 1); // denormalized operand
// regs->insert("fpstatus_ze", x86_regclass_flags, x86_flags_fpstatus, 2, 1); // zero divide
// regs->insert("fpstatus_oe", x86_regclass_flags, x86_flags_fpstatus, 3, 1); // overflow
// regs->insert("fpstatus_ue", x86_regclass_flags, x86_flags_fpstatus, 4, 1); // underflow
// regs->insert("fpstatus_pe", x86_regclass_flags, x86_flags_fpstatus, 5, 1); // precision
// regs->insert("fpstatus_ir", x86_regclass_flags, x86_flags_fpstatus, 7, 1); // interrupt request
// regs->insert("fpstatus_c4", x86_regclass_flags, x86_flags_fpstatus, 8, 1); // condition code
// regs->insert("fpstatus_c1", x86_regclass_flags, x86_flags_fpstatus, 9, 1); // condition code
// regs->insert("fpstatus_c2", x86_regclass_flags, x86_flags_fpstatus, 10, 1); // condition code
// regs->insert("fpstatus_top", x86_regclass_flags, x86_flags_fpstatus, 11, 3); // top of stack
// regs->insert("fpstatus_c3", x86_regclass_flags, x86_flags_fpstatus, 14, 1); // condition code
// regs->insert("fpstatus_b", x86_regclass_flags, x86_flags_fpstatus, 15, 1); // busy
//
// // Floating-point control register
// regs->insert("fpctl", x86_regclass_flags, x86_flags_fpctl, 0, 16);
// regs->insert("fpctl_im", x86_regclass_flags, x86_flags_fpctl, 0, 1); // invalid operation
// regs->insert("fpctl_dm", x86_regclass_flags, x86_flags_fpctl, 1, 1); // denormalized operand
// regs->insert("fpctl_zm", x86_regclass_flags, x86_flags_fpctl, 2, 1); // zero divide
// regs->insert("fpctl_om", x86_regclass_flags, x86_flags_fpctl, 3, 1); // overflow
// regs->insert("fpctl_um", x86_regclass_flags, x86_flags_fpctl, 4, 1); // underflow
// regs->insert("fpctl_pm", x86_regclass_flags, x86_flags_fpctl, 5, 1); // precision
// regs->insert("fpctl_m", x86_regclass_flags, x86_flags_fpctl, 7, 1); // interrupt mask
// regs->insert("fpctl_pc", x86_regclass_flags, x86_flags_fpctl, 8, 2); // precision control
// regs->insert("fpctl_rc", x86_regclass_flags, x86_flags_fpctl, 10, 2); // rounding control
// regs->insert("fpctl_ic", x86_regclass_flags, x86_flags_fpctl, 12, 1); // infinity control
// }
// return regs;
//}
//
//
///** Intel 80486 registers.
// *
// * The 80486 has the same registers as the 80386 with '387 co-processor but adds a new flag to the "eflags" register. */
//const RegisterDictionary *
//RegisterDictionary::dictionary_i486()
//{
// static RegisterDictionary *regs = NULL;
// if (!regs) {
// regs = new RegisterDictionary("i486");
// regs->insert(dictionary_i386_387());
// regs->insert("ac", x86_regclass_flags, x86_flags_status, 18, 1); /* alignment check system flag */
// }
// return regs;
//}
//
///** Intel Pentium registers.
// *
// * The Pentium has the same registers as the 80486 but adds a few flags to the "eflags" register and MMX registers. */
//const RegisterDictionary *
//RegisterDictionary::dictionary_pentium()
//{
// static RegisterDictionary *regs = NULL;
// if (!regs) {
// regs = new RegisterDictionary("pentium");
// regs->insert(dictionary_i486());
//
// /* Additional flags */
// regs->insert("vif", x86_regclass_flags, x86_flags_status, 19, 1); /* virtual interrupt flag */
// regs->insert("vip", x86_regclass_flags, x86_flags_status, 20, 1); /* virt interrupt pending */
// regs->insert("id", x86_regclass_flags, x86_flags_status, 21, 1); /* ident system flag */
//
// /* The MMi registers are aliases for the ST(i) registers but are absolute rather than relative to the top of the
// * stack. We're creating the static definitions, so MMi will point to the same storage as ST(i) for 0<=i<=7. Note that
// * a write to one of the 64-bit MMi registers causes the high-order 16 bits of the corresponding ST(j) register to be
// * set to all ones to indicate a NaN value. */
// regs->insert("mm0", x86_regclass_st, x86_st_0, 0, 64);
// regs->insert("mm1", x86_regclass_st, x86_st_1, 0, 64);
// regs->insert("mm2", x86_regclass_st, x86_st_2, 0, 64);
// regs->insert("mm3", x86_regclass_st, x86_st_3, 0, 64);
// regs->insert("mm4", x86_regclass_st, x86_st_4, 0, 64);
// regs->insert("mm5", x86_regclass_st, x86_st_5, 0, 64);
// regs->insert("mm6", x86_regclass_st, x86_st_6, 0, 64);
// regs->insert("mm7", x86_regclass_st, x86_st_7, 0, 64);
// }
// return regs;
//}
//
///** Intel Pentium III registers.
// *
// * The Pentium III has the same register set as the Pentium but adds the xmm0 through xmm7 registers for the SSE instruction
// * set. */
//const RegisterDictionary *
//RegisterDictionary::dictionary_pentiumiii()
//{
// static RegisterDictionary *regs = NULL;
// if (!regs) {
// regs = new RegisterDictionary("pentiumiii");
// regs->insert(dictionary_pentium());
// regs->insert("xmm0", x86_regclass_xmm, 0, 0, 128);
// regs->insert("xmm1", x86_regclass_xmm, 1, 0, 128);
// regs->insert("xmm2", x86_regclass_xmm, 2, 0, 128);
// regs->insert("xmm3", x86_regclass_xmm, 3, 0, 128);
// regs->insert("xmm4", x86_regclass_xmm, 4, 0, 128);
// regs->insert("xmm5", x86_regclass_xmm, 5, 0, 128);
// regs->insert("xmm6", x86_regclass_xmm, 6, 0, 128);
// regs->insert("xmm7", x86_regclass_xmm, 7, 0, 128);
//
// /** SSE status and control register. */
// regs->insert("mxcsr", x86_regclass_flags, x86_flags_mxcsr, 0, 32);
// regs->insert("mxcsr_ie", x86_regclass_flags, x86_flags_mxcsr, 0, 1); // invalid operation flag
// regs->insert("mxcsr_de", x86_regclass_flags, x86_flags_mxcsr, 1, 1); // denormal flag
// regs->insert("mxcsr_ze", x86_regclass_flags, x86_flags_mxcsr, 2, 1); // divide by zero flag
// regs->insert("mxcsr_oe", x86_regclass_flags, x86_flags_mxcsr, 3, 1); // overflow flag
// regs->insert("mxcsr_ue", x86_regclass_flags, x86_flags_mxcsr, 4, 1); // underflow flag
// regs->insert("mxcsr_pe", x86_regclass_flags, x86_flags_mxcsr, 5, 1); // precision flag
// regs->insert("mxcsr_daz", x86_regclass_flags, x86_flags_mxcsr, 6, 1); // denormals are zero
// regs->insert("mxcsr_im", x86_regclass_flags, x86_flags_mxcsr, 7, 1); // invalid operation mask
// regs->insert("mxcsr_dm", x86_regclass_flags, x86_flags_mxcsr, 8, 1); // denormal mask
// regs->insert("mxcsr_zm", x86_regclass_flags, x86_flags_mxcsr, 9, 1); // divide by zero mask
// regs->insert("mxcsr_om", x86_regclass_flags, x86_flags_mxcsr, 10, 1); // overflow mask
// regs->insert("mxcsr_um", x86_regclass_flags, x86_flags_mxcsr, 11, 1); // underflow mask
// regs->insert("mxcsr_pm", x86_regclass_flags, x86_flags_mxcsr, 12, 1); // precision mask
// regs->insert("mxcsr_r", x86_regclass_flags, x86_flags_mxcsr, 13, 2); // rounding mode
// regs->insert("mxcsr_fz", x86_regclass_flags, x86_flags_mxcsr, 15, 1); // flush to zero
// }
// return regs;
//}
//
///** Intel Pentium 4 registers. */
//const RegisterDictionary *
//RegisterDictionary::dictionary_pentium4()
//{
// static RegisterDictionary *regs = NULL;
// if (!regs) {
// regs = new RegisterDictionary("pentium4");
// regs->insert(dictionary_pentiumiii());
// }
// return regs;
//}
//


/** AMDGPU Registers
* Scalar Registers : total 104 registers of 32 bits
*
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