Rename cmpxch -> cmpxchg

It's the correct spelling of the mnemonic.
dyninst · Nov 24, 2023 · 6d4c305 · 6d4c305
1 parent b38c88f
commit 6d4c305
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Showing 5 changed files with 8 additions and 8 deletions.
diff --git a/common/src/arch-x86.C b/common/src/arch-x86.C
@@ -936,7 +936,7 @@ COMMON_EXPORT dyn_hash_map<entryID, std::string> entryNames_IAPI = map_list_of
   (e_cmpsd, "cmpsd")
   (e_cmpss, "cmpss")
   (e_cmpsw, "cmpsw")
-  (e_cmpxch, "cmpxch")
+  (e_cmpxchg, "cmpxchg")
   (e_cmpxch8b, "cmpxch8b")
   (e_comisd, "comisd")
   (e_comiss, "comiss")
@@ -2083,7 +2083,7 @@ void ia32_instruction::initFlagTable(dyn_hash_map<entryID, flagInfo>& flagTable_
   flagTable_[e_cmpsd] = flagInfo(vector<Dyninst::MachRegister>(), standardFlags);
   flagTable_[e_cmpss] = flagInfo(vector<Dyninst::MachRegister>(), standardFlags);
   flagTable_[e_cmpsw] = flagInfo(vector<Dyninst::MachRegister>(), standardFlags);
-  flagTable_[e_cmpxch] = flagInfo(vector<Dyninst::MachRegister>(), standardFlags);
+  flagTable_[e_cmpxchg] = flagInfo(vector<Dyninst::MachRegister>(), standardFlags);
   flagTable_[e_cmpxch8b] = flagInfo(vector<Dyninst::MachRegister>(), list_of(x86::zf));
   flagTable_[e_comisd] = flagInfo(vector<Dyninst::MachRegister>(), standardFlags);
   flagTable_[e_comiss] = flagInfo(vector<Dyninst::MachRegister>(), standardFlags);
@@ -2734,8 +2734,8 @@ static ia32_entry twoByteMap[256] = {
   // Assuming this is used with LOCK prefix, the destination gets a write anyway
   // This is not the case without lock prefix, but I ignore that case
   // Also, given that the 3rd operand is a register I ignore that it may be written
-  { e_cmpxch, t_done, 0, true, { Eb, Gb, AL }, 0, s1RW2R3R | (fCMPXCH << FPOS), s2I },
-  { e_cmpxch, t_done, 0, true, { Ev, Gv, eAX }, 0, s1RW2R3R | (fCMPXCH << FPOS), s2I },
+  { e_cmpxchg, t_done, 0, true, { Eb, Gb, AL }, 0, s1RW2R3R | (fCMPXCH << FPOS), s2I },
+  { e_cmpxchg, t_done, 0, true, { Ev, Gv, eAX }, 0, s1RW2R3R | (fCMPXCH << FPOS), s2I },
   { e_lss, t_done, 0, true, { SS, Gv, Mp }, 0, s1W2W3R, 0 },
   { e_btr, t_done, 0, true, { Ev, Gv, Zz }, 0, s1RW2R, 0 },
   { e_lfs, t_done, 0, true, { FS, Gv, Mp }, 0, s1W2W3R, 0 },

diff --git a/dataflowAPI/src/RoseInsnFactory.C b/dataflowAPI/src/RoseInsnFactory.C
@@ -158,7 +158,7 @@ void RoseInsnX86Factory::massageOperands(const Instruction &insn,
     // ROSE does not need implicit registers
     operands.resize(1);
     break;
-  case e_cmpxch:
+  case e_cmpxchg:
     operands.resize(2);
     break;
   case e_movsb:

diff --git a/dataflowAPI/src/convertOpcodes.C b/dataflowAPI/src/convertOpcodes.C
@@ -150,7 +150,7 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID
             return x86_cmpss;
         case e_cmpsw:
             return x86_cmpsw;
-        case e_cmpxch:
+        case e_cmpxchg:
             return x86_cmpxchg;
         case e_cmpxch8b:
             return x86_cmpxchg8b;

diff --git a/instructionAPI/src/InstructionCategories.C b/instructionAPI/src/InstructionCategories.C
@@ -90,7 +90,7 @@ namespace Dyninst
           case e_cmpsd:
           case e_cmpss:
           case e_cmpsw:
-          case e_cmpxch:
+          case e_cmpxchg:
           case e_cmpxch8b:
           case power_op_cmp:
           case power_op_cmpi:

diff --git a/instructionAPI/src/InstructionDecoder-x86.C b/instructionAPI/src/InstructionDecoder-x86.C
@@ -1789,7 +1789,7 @@ namespace Dyninst
                     case e_btc:
                     case e_btr:
                     case e_bts:
-                    case e_cmpxch:
+                    case e_cmpxchg:
                     case e_cmpxch8b:
                     case e_dec:
                     case e_inc: