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Added a method to get the target SgAsmExpression when executing
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write-back for load/store instructions
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@ssunny7
ssunny7 committed Oct 31, 2016
1 parent 84e671b commit 71de691
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Showing 2 changed files with 40 additions and 18 deletions.
55 changes: 37 additions & 18 deletions dataflowAPI/rose/semantics/DispatcherARM64.C
View file
Expand Up @@ -945,7 +945,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1002,7 +1002,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1059,7 +1059,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1116,7 +1116,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1173,7 +1173,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1230,7 +1230,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1287,7 +1287,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1345,7 +1345,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1402,7 +1402,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1459,7 +1459,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1516,7 +1516,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1573,7 +1573,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1630,7 +1630,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1687,7 +1687,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1744,7 +1744,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1801,7 +1801,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1858,7 +1858,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -1915,7 +1915,7 @@ namespace rose {
d->writeRegister(d->REG_SP, address);
}
else {
d->write(args[1], address);
d->write(d->getWriteBackTarget(args[1]), address);
}
}

Expand Down Expand Up @@ -2495,6 +2495,7 @@ namespace rose {
operators->isEqual(zVal, operators->number_(1, 0)),
operators->boolean_(true), operators->boolean_(false)),
operators->boolean_(false));
break;
case 5: result = operators->isEqual(nVal, vVal);
break;
case 6: result = operators->ite(operators->isEqual(nVal, vVal),
Expand Down Expand Up @@ -2755,6 +2756,24 @@ namespace rose {
//The third and fourth arguments will remain unused
state->writeMemory(addr, data, NULL, NULL, writeSize);
}

SgAsmExpression *
DispatcherARM64::getWriteBackTarget(SgAsmExpression *expr) {
SgAsmMemoryReferenceExpression *memoryExpression = isSgAsmMemoryReferenceExpression(expr);
ASSERT_not_null(memoryExpression);

SgAsmExpression *address = memoryExpression->get_address();
ASSERT_not_null(address);

if(isSgAsmBinaryAdd(address)) {
return isSgAsmBinaryAdd(address)->get_lhs();
} else {
SgAsmRegisterReferenceExpression *retval = isSgAsmRegisterReferenceExpression(address);
ASSERT_not_null(retval);

return retval;
}
}
} // namespace
} // namespace
} // namespace
Expand Down
3 changes: 3 additions & 0 deletions dataflowAPI/rose/semantics/DispatcherARM64.h
View file
Expand Up @@ -224,6 +224,9 @@ namespace rose {

/** */
void writeMemory(const BaseSemantics::SValuePtr &addr, size_t writeSize, const BaseSemantics::SValuePtr &data);

/** */
SgAsmExpression *getWriteBackTarget(SgAsmExpression *expr);
};

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
Expand Down

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