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Merge branch 'VEX' of https://github.com/dyninst/dyninst into dyninst…
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…-VEX

Conflicts:
	common/src/arch-x86.C
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@mxz297
mxz297 committed Jun 14, 2016
2 parents 2c99375 + 73da5f1 commit 78b4102
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Showing 3 changed files with 28 additions and 41 deletions.
3 changes: 3 additions & 0 deletions common/h/entryIDs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -224,6 +224,8 @@ enum entryID {
e_fprem,
e_frstor,
e_fsave,
e_xbegin,
e_xabort,
e_fst,
e_fstcw,
e_fstenv,
Expand Down Expand Up @@ -1065,6 +1067,7 @@ enum entryID {
e_vpmultishiftqb,
e_vpmadd52luq,
e_vpmadd52huq,
e_vptestmd,
e_vptestnmd,
e_vptestnmb,
e_vpternlogd,
Expand Down
64 changes: 24 additions & 40 deletions common/src/arch-x86.C
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Original file line number Diff line number Diff line change
Expand Up @@ -303,7 +303,7 @@ enum { /** AUTOGENERATED */
SSEB24_66, SSEB24_F3,
SSEB25_66, SSEB25_F3,
SSEB26_F3,
SSEB27_F3,
SSEB27_66, SSEB27_F3,
SSEB28_66, SSEB28_F3,
SSEB29_66, SSEB29_F3,
SSEB2A_66, SSEB2A_F3,
Expand Down Expand Up @@ -499,14 +499,11 @@ enum {
};

// VEX table
/** START_DYNINST_TABLE_DEF(vexl_table, VEXL, NO) */
enum {
VEXL00=0
};

// REX table
enum {
REX00=0
VEXL00 = 0
};
/** END_DYNINST_TABLE_DEF */

/* Vex instructions that need extra decoding with the W bit */
/** START_DYNINST_TABLE_DEF(vex_w_table, VEXW, NO) */
Expand Down Expand Up @@ -908,6 +905,8 @@ COMMON_EXPORT dyn_hash_map<entryID, std::string> entryNames_IAPI = map_list_of
(e_fxch, "fxch")
(e_fxrstor, "fxrstor")
(e_fxsave, "fxsave")
(e_xbegin, "xbegin")
(e_xabort, "xabort")
(e_haddpd, "haddpd")
(e_haddps, "haddps")
(e_hlt, "hlt")
Expand Down Expand Up @@ -1723,6 +1722,7 @@ COMMON_EXPORT dyn_hash_map<entryID, std::string> entryNames_IAPI = map_list_of
(e_vpsubusb, "vpsubusb")
(e_vpsubusw, "vpsubusw")
(e_vpsubw, "vpsubw")
(e_vptestmd, "vptestmd")
(e_vptestnmd, "vptestnmd")
(e_vptestnmb, "vptestnmb")
(e_vpternlogd, "vpternlogd")
Expand Down Expand Up @@ -2189,7 +2189,7 @@ true, { Eb, Gb, Zz }, 0, s1RW2R },
{ e_pushad, t_done, 0, false, { GPRS, eSP, Zz }, 0, s1R2RW },
{ e_popad, t_done, 0, false, { GPRS, eSP, Zz }, 0, s1W2RW },
{ e_bound, t_done, 0, true, { Gv, Ma, Zz }, 0, s1R2R }, // or VEX
{ e_No_Entry, t_rex, REX00, false, { Zz, Zz, Zz }, 0, 0 },
{ e_arpl, t_done, 0, true, { Ew, Gw, Zz }, 0, s1R2R }, /* No REX */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }, // PREFIX_SEG_OVR
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }, // PREFIX_SEG_OVR
{ e_No_Entry, t_ill, 2, false, { Zz, Zz, Zz }, 0, 0 }, /* operand size prefix (PREFIX_OPR_SZ) (depricated: prefixedSSE)*/
Expand Down Expand Up @@ -3588,14 +3588,14 @@ static ia32_entry groupMap[][8] = {
/* group 10 is all illegal */

{ /* group 11, opcodes defined in one byte map */
{ e_mov, t_done, 0, true, { Zz, Zz, Zz }, 0, sNONE },
{ e_No_Entry, t_ill, 0, true, { Zz, Zz, Zz }, 0, 0 },
{ e_mov, t_done, 0, true, { Ev, Gv, Zz }, 0, s1W2R },
{ e_No_Entry, t_ill, 0, true, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, true, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, true, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, true, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, true, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, true, { Zz, Zz, Zz }, 0, 0 },
{ e_xbegin, t_done, 0, false, { Jz, Zz, Zz }, 0, s1R },
}

};
Expand Down Expand Up @@ -4889,7 +4889,7 @@ static ia32_entry sseMapBis[][5] = {
}, { /* SSEB27 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_sse_bis_mult, SSEB27_F3, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_sse_bis_mult, SSEB27_66, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSEB28 */
Expand Down Expand Up @@ -5608,7 +5608,7 @@ static ia32_entry sseMapTer[][3] =
{ e_roundss, t_done, 0, true, { Vss, Wss, Ib }, 0, s1W2R3R },
}, { /* SSET0B */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_sse_ter_mult, SSET0B_66, false, { Zz, Zz, Zz }, 0, 0 },
{ e_roundsd, t_sse_ter_mult, SSET0B_66, true, { Vsd, Wsd, Ib }, 0, s1W2R3R },
{ e_roundsd, t_done, 0, true, { Vsd, Wsd, Ib }, 0, s1W2R3R },
}, { /* SSET0C */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
Expand All @@ -5619,9 +5619,9 @@ static ia32_entry sseMapTer[][3] =
{ e_No_Entry, t_vexw, VEXW94, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_vexw, VEXW94, false, { Zz, Zz, Zz }, 0, 0 }
}, { /* SSET0E */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_pblendw, t_done, 0, true, { Vdq, Wdq, Ib }, 0, s1RW2R3R },
{ e_pblendw, t_done, 0, true, { Vdq, Wdq, Ib }, 0, s1RW2R3R }
}, { /* SSET0F */
{ e_palignr, t_done, 0, true, { Pq, Qq, Ib }, 0, s1RW2R3R },
{ e_palignr, t_sse_ter_mult, SSET0F_66, true, { Pq, Qq, Ib }, 0, s1RW2R3R },
Expand Down Expand Up @@ -5800,12 +5800,12 @@ static ia32_entry sseMapTer[][3] =
{ e_pcmpestri, t_done, 0, true, { Vdq, Wdq, Ib }, 0, s1R2R3R }
}, { /* SSET62 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_pcmpistrm, t_done, 0, true, { Vdq, Wdq, Ib }, 0, s1R2R3R },
{ e_pcmpistrm, t_done, 0, true, { Vdq, Wdq, Ib }, 0, s1R2R3R }
}, { /* SSET63 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_pcmpistri, t_done, 0, true, { Vdq, Wdq, Ib }, 0, s1R2R3R },
{ e_pcmpistri, t_done, 0, true, { Vdq, Wdq, Ib }, 0, s1R2R3R },
}, { /* SSET66 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_sse_ter_mult, SSET66_66, false, { Zz, Zz, Zz }, 0, 0 },
Expand Down Expand Up @@ -6808,6 +6808,10 @@ ia32_entry sseMapBisMult[][3] =
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vptestnmb, t_done, 0, true, { VK, Hps, Wps }, 0, s1W2R3R }
}, { /* SSEB27_66 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vptestmd, t_done, 0, true, { VK, Hps, Wps }, 0, s1W2R3R },
{ e_vptestmd, t_done, 0, true, { VK, Hps, Wps }, 0, s1W2R3R },
}, { /* SSEB27_F3 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
Expand Down Expand Up @@ -7323,7 +7327,7 @@ ia32_entry sseMapTerMult[][3] =
{ e_vrndscalesd, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R }
}, { /* SSET0C_66 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
{ e_vblendps, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R },
{ e_vblendps, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R }
}, { /* SSET0F_66 */
{ e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0 },
Expand Down Expand Up @@ -7617,21 +7621,15 @@ static ia32_entry ssegrpMap_VEX[][2] = {
* index: found by using opcode lookups in the oneByteMap.
* L: The l bit of the prefix. L=1 is YMM registers, L=0 is XMM registers
*/
/** START_DYNINST_TABLE_VERIFICATION(vexl_table) */
static struct ia32_entry vex2Map[][2] =
{
{ /* VEX200 */
{ /* VEXL00 */
{ e_vzeroupper, t_done, 0, false, { Zz, Zz, Zz }, 0, sNONE }, /* L = 0 */
{ e_vzeroall, t_done, 0, false, { Zz, Zz, Zz }, 0, sNONE } /* L = 1 */
}
};

static struct ia32_entry rexMap[][2] =
{
{
{ e_arpl, t_done, 0, true, { Ew, Gw, Zz }, 0, s1R2R }, /* No REX */
{ e_movsxd, t_done, 0, true, { Gv, Ed, Zz }, 0, s1W2R }, /* HAS REX */
}
};
/** END_DYNINST_TABLE_VERIFICATION */

/**
* VEX (3 byte) prefixed instructions
Expand Down Expand Up @@ -8670,20 +8668,6 @@ ia32_instruction& ia32_decode(unsigned int capa, const unsigned char* addr, ia32

nxtab = gotit->otable;
break;

case t_rex:
idx = gotit->tabidx;
/* Does this instruction have a REX prefix? */
if(pref.getPrefix(4))
{
gotit = &rexMap[idx][1];
} else {
gotit = &rexMap[idx][0];
}

nxtab = gotit->otable;
break;

case t_ill:
#ifdef VEX_DEBUG
if(pref.vex_present)
Expand Down Expand Up @@ -8719,7 +8703,7 @@ ia32_instruction& ia32_decode(unsigned int capa, const unsigned char* addr, ia32
/* make adjustments for instruction redefined in 64-bit mode */
if(mode_64)
{
// ia32_translate_for_64(&gotit);
ia32_translate_for_64(&gotit);
}

/* Do the operand decoding */
Expand Down
2 changes: 1 addition & 1 deletion common/src/arch-x86.h
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Original file line number Diff line number Diff line change
Expand Up @@ -603,7 +603,7 @@ enum {
t_ill=0, t_oneB, t_twoB, t_threeB, t_threeB2, t_prefixedSSE, t_coprocEsc,
t_grp, t_sse, t_sse_mult, t_sse_bis, t_sse_bis_mult,
t_sse_ter, t_sse_ter_mult, t_grpsse, t_3dnow, t_vexl, t_vexw, t_sse_vex_mult,
t_rex, t_done=99
t_done=99
};

// registers used for memory access
Expand Down

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