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Finish most of the Power 8 VSX instruction decoding
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@mxz297
mxz297 committed Oct 24, 2018
1 parent e0b4778 commit aad240c
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Showing 4 changed files with 30 additions and 22 deletions.
8 changes: 6 additions & 2 deletions common/h/entryIDs.h
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Expand Up @@ -1365,7 +1365,6 @@ enum entryID {
power_op_rfi,
power_op_sreq,
power_op_frsqrte,
power_op_mffs,
power_op_lwz,
power_op_lfqu,
power_op_and,
Expand Down Expand Up @@ -2215,6 +2214,11 @@ enum entryID {
power_op_mffscrn,
power_op_mffscrni,
power_op_mffsl,
power_op_vnmsubfp,
power_op_vrlh,
power_op_vminfp,
power_op_bcdsr,
/*
power_op_
power_op_
power_op_
Expand All @@ -2229,7 +2233,7 @@ enum entryID {
power_op_
power_op_
power_op_

*/
// ***********
// Steve note:
// aarch64 opcode IDs.
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32 changes: 16 additions & 16 deletions instructionAPI/src/InstructionDecoder-power.C
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Expand Up @@ -571,44 +571,44 @@ namespace Dyninst

void InstructionDecoder_power::UIM()
{
assert(0);
insn_in_progress->appendOperand(makeRTExpr(), false, true);
fprintf(stderr, "Unimplemented operand type UIM. Please create an issue at https://github.com/dyninst/dyninst/issues\n");
}
void InstructionDecoder_power::SIM()
{
assert(0);
insn_in_progress->appendOperand(makeRTExpr(), false, true);
fprintf(stderr, "Unimplemented operand type SIM. Please create an issue at https://github.com/dyninst/dyninst/issues\n");
}

void InstructionDecoder_power::DCMX()
{
assert(0);
insn_in_progress->appendOperand(makeRTExpr(), false, true);
fprintf(stderr, "Unimplemented operand type DCMX. Please create an issue at https://github.com/dyninst/dyninst/issues\n");
}
void InstructionDecoder_power::RO()
{
assert(0);
insn_in_progress->appendOperand(makeRTExpr(), false, true);
fprintf(stderr, "Unimplemented operand type RO. Please create an issue at https://github.com/dyninst/dyninst/issues\n");
}
void InstructionDecoder_power::R()
{
assert(0);
insn_in_progress->appendOperand(makeRTExpr(), false, true);
fprintf(stderr, "Unimplemented operand type R. Please create an issue at https://github.com/dyninst/dyninst/issues\n");
}
void InstructionDecoder_power::RMC()
{
assert(0);
insn_in_progress->appendOperand(makeRTExpr(), false, true);
fprintf(stderr, "Unimplemented operand type RMC. Please create an issue at https://github.com/dyninst/dyninst/issues\n");
}
void InstructionDecoder_power::EX()
{
assert(0);
insn_in_progress->appendOperand(makeRTExpr(), false, true);
fprintf(stderr, "Unimplemented operand type EX. Please create an issue at https://github.com/dyninst/dyninst/issues\n");
}
void InstructionDecoder_power::SHB()
{
assert(0);
insn_in_progress->appendOperand(makeRTExpr(), false, true);
fprintf(stderr, "Unimplemented operand type SHB. Please create an issue at https://github.com/dyninst/dyninst/issues\n");
}
void InstructionDecoder_power::PS()
{
fprintf(stderr, "Unimplemented operand type PS. Please create an issue at https://github.com/dyninst/dyninst/issues\n");
}
void InstructionDecoder_power::CY()
{
fprintf(stderr, "Unimplemented operand type CY. Please create an issue at https://github.com/dyninst/dyninst/issues\n");
}

/***** END: For new vector instructions *****/
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4 changes: 4 additions & 0 deletions instructionAPI/src/InstructionDecoder-power.h
View file
Expand Up @@ -182,6 +182,10 @@ namespace Dyninst {
void RMC();
void EX();
void SHB();
void SIX();
void PS();
void CY();



const power_entry& extended_op_0();
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8 changes: 4 additions & 4 deletions instructionAPI/src/power_opcode_tables.C
View file
Expand Up @@ -511,26 +511,26 @@ extended_op_4[1537] = power_entry(power_op_bcdadd, "bcdadd", NULL, list_of(fn(VR
//extended_op_4[1538] = power_entry(power_op_extended, "extended", fn(extended_op_4_1538), operandSpec()));


extended_op_4[1540] = power_entry(power_op_mfvscr, "mfvscr", NULL, list_of((fn(VRT)));
extended_op_4[1540] = power_entry(power_op_mfvscr, "mfvscr", NULL, list_of((fn(VRT))));
extended_op_4[1542] = power_entry(power_op_vcmpgtub, "vcmpgtub", NULL, list_of(fn(VRT))(fn(VRA))(fn(VRB))(fn(Rc)));
extended_op_4[1544] = power_entry(power_op_vsum4ubs, "vsum4ubs", NULL, list_of(fn(VRT))(fn(VRA))(fn(VRB)));
extended_op_4[1549] = power_entry(power_op_vextublx, "vextublx", NULL, list_of(fn(RT))(fn(RA))(fn(VRB)));
extended_op_4[1600] = power_entry(power_op_vsubuhs, "vsubuhs", NULL, list_of(fn(VRT))(fn(VRA))(fn(VRB)));
extended_op_4[1601] = power_entry(power_op_bcdsub, "bcdsub", NULL, list_of(fn(VRT))(fn(VRA))(fn(VRB))(fn(PS)));
extended_op_4[1604] = power_entry(power_op_mtvscr, "mtvscr", NULL, list_of((fn(VRB)));
extended_op_4[1604] = power_entry(power_op_mtvscr, "mtvscr", NULL, list_of((fn(VRB))));
extended_op_4[1606] = power_entry(power_op_vcmpgtuh, "vcmpgtuh", NULL, list_of(fn(VRT))(fn(VRA))(fn(VRB))(fn(Rc)));
extended_op_4[1608] = power_entry(power_op_vsum4shs, "vsum4shs", NULL, list_of(fn(VRT))(fn(VRA))(fn(VRB)));
extended_op_4[1613] = power_entry(power_op_vextuhlx, "vextuhlx", NULL, list_of(fn(RT))(fn(RA))(fn(VRB)));
extended_op_4[1614] = power_entry(power_op_vupkhsw, "vupkhsw", NULL, list_of(fn(VRT))(fn(VRB)));
extended_op_4[1664] = power_entry(power_op_vsubuws, "vsubuws", NULL, list_of(fn(VRT))(fn(VRA))(fn(VRB)));
extended_op_4[1666] = power_entry(power_op_vshasigmaw, "vshasigmaw", NULL, list_of(fn(VRT))(fn(VRA))(fn(ST))(fn(SIX)));
//extended_op_4[1666] = power_entry(power_op_vshasigmaw, "vshasigmaw", NULL, list_of(fn(VRT))(fn(VRA))(fn(ST))(fn(SIX)));
extended_op_4[1668] = power_entry(power_op_veqv, "veqv", NULL, list_of(fn(VRT))(fn(VRA))(fn(VRB)));
extended_op_4[1670] = power_entry(power_op_vcmpgtuw, "vcmpgtuw", NULL, list_of(fn(VRT))(fn(VRA))(fn(VRB))(fn(Rc)));
extended_op_4[1672] = power_entry(power_op_vsum2sws, "vsum2sws", NULL, list_of(fn(VRT))(fn(VRA))(fn(VRB)));
extended_op_4[1676] = power_entry(power_op_vmrgow, "vmrgow", NULL, list_of(fn(VRT))(fn(VRA))(fn(VRB)));
extended_op_4[1677] = power_entry(power_op_vextuwlx, "vextuwlx", NULL, list_of(fn(RT))(fn(RA))(fn(VRB)));
extended_op_4[1729] = power_entry(power_op_bcds, "bcds", NULL, list_of(fn(VRT))(fn(VRA))(fn(VRB))(fn(PS)));
extended_op_4[1730] = power_entry(power_op_vshasigmad, "vshasigmad", NULL, list_of(fn(VRT))(fn(VRA))(fn(ST))(fn(SIX)));
//extended_op_4[1730] = power_entry(power_op_vshasigmad, "vshasigmad", NULL, list_of(fn(VRT))(fn(VRA))(fn(ST))(fn(SIX)));
extended_op_4[1732] = power_entry(power_op_vsrd, "vsrd", NULL, list_of(fn(VRT))(fn(VRA))(fn(VRB)));
extended_op_4[1735] = power_entry(power_op_vcmpgtub, "vcmpgtub", NULL, list_of(fn(VRT))(fn(VRA))(fn(VRB))(fn(Rc)));
extended_op_4[1742] = power_entry(power_op_vupklsw, "vupklsw", NULL, list_of(fn(VRT))(fn(VRB)));
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