Codegen functions for ADD variants

Added two new codegen functions for the ADD (immediate) and ADD (shifted register) variants of the ADD instruction for ARM64.
dyninst · Mar 31, 2017 · b6608b6 · b6608b6
1 parent b9a2395
commit b6608b6
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Showing 3 changed files with 51 additions and 7 deletions.
diff --git a/common/src/arch-aarch64.h b/common/src/arch-aarch64.h
@@ -62,6 +62,9 @@ namespace NS_aarch64 {
 #define BRegOp          0xD61F
 #define NOOP            0xD503201F
 
+#define ADDShiftOp      0x0B
+#define ADDImmOp        0x11
+
 #define STRImmOp        0x1C0
 #define LDRImmOp        0x1C2
 #define STRFPImmOp      0x1E0

diff --git a/dyninstAPI/src/codegen-aarch64.C b/dyninstAPI/src/codegen-aarch64.C
@@ -185,13 +185,53 @@ void insnCodeGen::generateBranchViaTrap(codeGen &gen, Address from, Address to,
     }
 }
 
-void insnCodeGen::generateAddReg (codeGen & gen, int op, Register rt,
-				   Register ra, Register rb)
-{
-    assert(0);
+void insnCodeGen::generateAddShifted(codeGen &gen, int shift, int imm6, Register rm, Register rn, Register rd, bool is64bit) {
     instruction insn;
     insn.clear();
 
+    //Set bit 31 to 1 if using 64-bit registers
+    if(is64bit)
+        INSN_SET(insn, 31, 31, 1);
+    //Set opcode
+    INSN_SET(insn, 24, 30, ADDShiftOp);
+
+    //Set shift field
+    assert(shift >= 0 && shift <= 3);
+    INSN_SET(insn, 22, 23, (shift & 0x3));
+
+    //Set imm6 field
+    assert(imm6 >= 0 && imm6 < (is64bit ? 64 : 32));
+    INSN_SET(insn, 10, 15, imm6);
+
+    //Set registers
+    INSN_SET(insn, 0, 4, rd);
+    INSN_SET(insn, 5, 9, rn);
+    INSN_SET(insn, 16, 20, rm);
+
+    insnCodeGen::generate(gen, insn);
+}
+
+void insnCodeGen::generateAddImmediate(codeGen &gen, int shift, int imm12, Register rn, Register rd, bool is64bit) {
+    instruction insn;
+    insn.clear();
+
+    //Set bit 31 to 1 if using 64-bit registers
+    if(is64bit)
+        INSN_SET(insn, 31, 31, 1);
+    //Set opcode
+    INSN_SET(insn, 24, 30, ADDImmOp);
+
+    //Set shift field
+    assert(shift >= 0 && shift <= 3);
+    INSN_SET(insn, 22, 23, (shift & 0x3));
+
+    //Set imm12 field
+    INSN_SET(insn, 10, 21, imm12);
+
+    //Set registers
+    INSN_SET(insn, 5, 9, rn);
+    INSN_SET(insn, 5, 9, rd);
+
     insnCodeGen::generate(gen, insn);
 }
 

diff --git a/dyninstAPI/src/codegen-aarch64.h b/dyninstAPI/src/codegen-aarch64.h
@@ -99,9 +99,6 @@ class insnCodeGen {
     static void generateStoreReg64(codeGen &gen, Register rs,
                                    Register ra, Register rb);
 
-    static void generateAddReg(codeGen &gen, int op,
-                               Register rt, Register ra, Register rb);
-
     static void generateLShift(codeGen &gen, Register rs,
                                int shift, Register ra);
 
@@ -143,6 +140,10 @@ class insnCodeGen {
 
     /** *** **/
 
+    static void generateAddShifted(codeGen &gen, int shift, int imm6, Register rm, Register rn, Register rd, bool is64bit);
+
+    static void generateAddImmediate(codeGen &gen, int shift, int imm12, Register rn, Register rd, bool is64bit);
+
     static void generateMove(codeGen &gen, int imm16, int shift, Register rd, MoveOp movOp);
 
     static void generateMoveSP(codeGen &gen, Register rn, Register rd, bool is64bit);