Add the memory-management registers

The processor provides four memory-management registers (GDTR, LDTR, IDTR, and TR) that specify the locations of the data structures which control segmented memory management. See Section 2.4 in Volume 3 of the Intel 64 and IA-32 Architectures Software Developer’s Manual from June 2021 for details.
dyninst · Nov 28, 2023 · d36550c · d36550c
1 parent 5ac2236
commit d36550c
Show file tree

Hide file tree

Showing 3 changed files with 356 additions and 333 deletions.
diff --git a/common/h/registers/x86_64_regs.h b/common/h/registers/x86_64_regs.h
@@ -104,6 +104,10 @@ namespace Dyninst { namespace x86_64 {
   const signed int BASEGS = 0x3; // G Segment register
   const signed int BASECS = 0x4; // Code Segment register
   const signed int BASEES = 0x5; // Extended data Segment register
+  const signed int BASEGD = 0x6; // Global Descriptor Table
+  const signed int BASELD = 0x7; // Local Descriptor Table
+  const signed int BASEID = 0X8; // Interrupt Descriptor Table
+  const signed int BASETR = 0x9; // Task Register
 
   /* Base IDs for each bit in RFLAGS */
   const signed int CF    = x86::CF;    // Carry Flag
@@ -239,6 +243,10 @@ namespace Dyninst { namespace x86_64 {
   DEF_REGISTER(        gs, BASEGS |  FULL |   SEG | Arch_x86_64, "x86_64");
   DEF_REGISTER(        cs, BASECS |  FULL |   SEG | Arch_x86_64, "x86_64");
   DEF_REGISTER(        ss, BASESS |  FULL |   SEG | Arch_x86_64, "x86_64");
+  DEF_REGISTER(      gdtr, BASEGD | W_REG |   SEG | Arch_x86_64, "x86_64");
+  DEF_REGISTER(      ldtr, BASELD | W_REG |   SEG | Arch_x86_64, "x86_64");
+  DEF_REGISTER(      idtr, BASEID | W_REG |   SEG | Arch_x86_64, "x86_64");
+  DEF_REGISTER(        tr, BASETR | W_REG |   SEG | Arch_x86_64, "x86_64");
 
   DEF_REGISTER(       cr0,    0x0 |  FULL |   CTL | Arch_x86_64, "x86_64");
   DEF_REGISTER(       cr1,    0x1 |  FULL |   CTL | Arch_x86_64, "x86_64");

diff --git a/common/h/registers/x86_regs.h b/common/h/registers/x86_regs.h
@@ -99,6 +99,10 @@ namespace Dyninst { namespace x86 {
   const signed int BASEGS = 0x3; // G Segment register
   const signed int BASECS = 0x4; // Code Segment register
   const signed int BASEES = 0x5; // Extended data Segment register
+  const signed int BASEGD = 0x6; // Global Descriptor Table
+  const signed int BASELD = 0x7; // Local Descriptor Table
+  const signed int BASEID = 0X8; // Interrupt Descriptor Table
+  const signed int BASETR = 0x9; // Task Register
 
   /* Base IDs for each bit in EFLAGS */
   const signed int CF    = 0x00;  // Carry Flag
@@ -169,6 +173,10 @@ namespace Dyninst { namespace x86 {
   DEF_REGISTER(        ss, BASESS | W_REG |   SEG | Arch_x86, "x86");
   DEF_REGISTER(        fs, BASEFS | W_REG |   SEG | Arch_x86, "x86");
   DEF_REGISTER(        gs, BASEGS | W_REG |   SEG | Arch_x86, "x86");
+  DEF_REGISTER(      gdtr, BASEGD | W_REG |   SEG | Arch_x86, "x86");
+  DEF_REGISTER(      ldtr, BASELD | W_REG |   SEG | Arch_x86, "x86");
+  DEF_REGISTER(      idtr, BASEID | W_REG |   SEG | Arch_x86, "x86");
+  DEF_REGISTER(        tr, BASETR | W_REG |   SEG | Arch_x86, "x86");
 
   DEF_REGISTER(     flags,  FLAGS |  FULL |  FLAG | Arch_x86, "x86");
   DEF_REGISTER(        cf,     CF |   BIT |  FLAG | Arch_x86, "x86");