Added pseudocode extractor extract and instruction pseudocode files

ISA_ps contains one file for each instruction in the XML specification,
with each file containing the pseudocode for that instruction
extracted from the specification by the script.

instructionAPI/ISA_ps/abs_advsimd

@@ -0,0 +1,17 @@
+##abs_advsimd_execute
+CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    end
+    Elem[result, e, esize] = element<esize-1:0>;                
+
+V[d] = result;
+@@

instructionAPI/ISA_ps/adc

@@ -0,0 +1,18 @@
+##adc_execute
+bits(datasize) result;
+bits(datasize) operand1 = X[n];
+bits(datasize) operand2 = X[m];
+bits(4) nzcv;
+
+if sub_op then
+    operand2 = NOT(operand2);
+end
+
+(result, nzcv) = AddWithCarry(operand1, operand2, PSTATE.C);
+
+if setflags then 
+    PSTATE.<N,Z,C,V> = nzcv;
+end
+
+X[d] = result;
+@@

instructionAPI/ISA_ps/adcs

@@ -0,0 +1,18 @@
+##adcs_execute
+bits(datasize) result;
+bits(datasize) operand1 = X[n];
+bits(datasize) operand2 = X[m];
+bits(4) nzcv;
+
+if sub_op then
+    operand2 = NOT(operand2);
+end
+
+(result, nzcv) = AddWithCarry(operand1, operand2, PSTATE.C);
+
+if setflags then 
+    PSTATE.<N,Z,C,V> = nzcv;
+end
+
+X[d] = result;
+@@

instructionAPI/ISA_ps/add_addsub_ext

@@ -0,0 +1,26 @@
+##add_addsub_ext_execute
+bits(datasize) result;
+bits(datasize) operand1 = if n == 31 then SP[] else X[n];
+bits(datasize) operand2 = ExtendReg(m, extend_type, shift);
+bits(4) nzcv;
+bit carry_in;
+
+if sub_op then
+    operand2 = NOT(operand2);
+    carry_in = 1;
+else
+    carry_in = 0;
+end
+
+(result, nzcv) = AddWithCarry(operand1, operand2, carry_in);
+
+if setflags then 
+    PSTATE.<N,Z,C,V> = nzcv;
+end
+
+if d == 31 && !setflags then
+    SP[] = result;
+else
+    X[d] = result;
+end
+@@

instructionAPI/ISA_ps/add_addsub_imm

@@ -0,0 +1,26 @@
+##add_addsub_imm_execute
+bits(datasize) result;
+bits(datasize) operand1 = if n == 31 then SP[] else X[n];
+bits(datasize) operand2 = imm;
+bits(4) nzcv;
+bit carry_in;
+
+if sub_op then
+    operand2 = NOT(operand2);
+    carry_in = 1;
+else
+    carry_in = 0;
+end
+
+(result, nzcv) = AddWithCarry(operand1, operand2, carry_in);
+
+if setflags then 
+    PSTATE.<N,Z,C,V> = nzcv;
+end
+
+if d == 31 && !setflags then
+    SP[] = result;
+else
+    X[d] = result;
+end
+@@

instructionAPI/ISA_ps/add_addsub_shift

@@ -0,0 +1,22 @@
+##add_addsub_shift_execute
+bits(datasize) result;
+bits(datasize) operand1 = X[n];
+bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount);
+bits(4) nzcv;
+bit carry_in;
+
+if sub_op then
+    operand2 = NOT(operand2);
+    carry_in = 1;
+else
+    carry_in = 0;
+end
+
+(result, nzcv) = AddWithCarry(operand1, operand2, carry_in);
+
+if setflags then 
+    PSTATE.<N,Z,C,V> = nzcv;
+end
+
+X[d] = result;
+@@

instructionAPI/ISA_ps/add_advsimd

@@ -0,0 +1,19 @@
+##add_advsimd_execute
+CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+    end
+
+V[d] = result;
+@@

instructionAPI/ISA_ps/addhn_advsimd

@@ -0,0 +1,23 @@
+##addhn_advsimd_execute
+CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize)   result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    end
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+@@

instructionAPI/ISA_ps/addp_advsimd_pair

@@ -0,0 +1,5 @@
+##addp_advsimd_pair_execute
+CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(op, operand, esize);
+@@

instructionAPI/ISA_ps/addp_advsimd_vec

@@ -0,0 +1,16 @@
+##addp_advsimd_vec_execute
+CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+@@

instructionAPI/ISA_ps/adds_addsub_ext

@@ -0,0 +1,26 @@
+##adds_addsub_ext_execute
+bits(datasize) result;
+bits(datasize) operand1 = if n == 31 then SP[] else X[n];
+bits(datasize) operand2 = ExtendReg(m, extend_type, shift);
+bits(4) nzcv;
+bit carry_in;
+
+if sub_op then
+    operand2 = NOT(operand2);
+    carry_in = 1;
+else
+    carry_in = 0;
+end
+
+(result, nzcv) = AddWithCarry(operand1, operand2, carry_in);
+
+if setflags then 
+    PSTATE.<N,Z,C,V> = nzcv;
+end
+
+if d == 31 && !setflags then
+    SP[] = result;
+else
+    X[d] = result;
+end
+@@

instructionAPI/ISA_ps/adds_addsub_imm

@@ -0,0 +1,26 @@
+##adds_addsub_imm_execute
+bits(datasize) result;
+bits(datasize) operand1 = if n == 31 then SP[] else X[n];
+bits(datasize) operand2 = imm;
+bits(4) nzcv;
+bit carry_in;
+
+if sub_op then
+    operand2 = NOT(operand2);
+    carry_in = 1;
+else
+    carry_in = 0;
+end
+
+(result, nzcv) = AddWithCarry(operand1, operand2, carry_in);
+
+if setflags then 
+    PSTATE.<N,Z,C,V> = nzcv;
+end
+
+if d == 31 && !setflags then
+    SP[] = result;
+else
+    X[d] = result;
+end
+@@

instructionAPI/ISA_ps/adds_addsub_shift

@@ -0,0 +1,22 @@
+##adds_addsub_shift_execute
+bits(datasize) result;
+bits(datasize) operand1 = X[n];
+bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount);
+bits(4) nzcv;
+bit carry_in;
+
+if sub_op then
+    operand2 = NOT(operand2);
+    carry_in = 1;
+else
+    carry_in = 0;
+end
+
+(result, nzcv) = AddWithCarry(operand1, operand2, carry_in);
+
+if setflags then 
+    PSTATE.<N,Z,C,V> = nzcv;
+end
+
+X[d] = result;
+@@

instructionAPI/ISA_ps/addv_advsimd

@@ -0,0 +1,5 @@
+##addv_advsimd_execute
+CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(op, operand, esize);
+@@

instructionAPI/ISA_ps/adr

@@ -0,0 +1,9 @@
+##adr_execute
+bits(64) base = PC[];
+
+if page then
+    base<11:0> = Zeros(12);
+end
+
+X[d] = base + imm;
+@@

instructionAPI/ISA_ps/adrp

@@ -0,0 +1,9 @@
+##adrp_execute
+bits(64) base = PC[];
+
+if page then
+    base<11:0> = Zeros(12);
+end
+
+X[d] = base + imm;
+@@

instructionAPI/ISA_ps/aesd_advsimd

@@ -0,0 +1,14 @@
+##aesd_advsimd_execute
+CheckCryptoEnabled64();
+
+bits(128) operand1 = V[d];
+bits(128) operand2 = V[n];
+bits(128) result;
+result = operand1 EOR operand2;
+if decrypt then
+    result = AESInvSubBytes(AESInvShiftRows(result));
+else
+    result = AESSubBytes(AESShiftRows(result));
+
+V[d] = result;
+@@

instructionAPI/ISA_ps/aese_advsimd

@@ -0,0 +1,14 @@
+##aese_advsimd_execute
+CheckCryptoEnabled64();
+
+bits(128) operand1 = V[d];
+bits(128) operand2 = V[n];
+bits(128) result;
+result = operand1 EOR operand2;
+if decrypt then
+    result = AESInvSubBytes(AESInvShiftRows(result));
+else
+    result = AESSubBytes(AESShiftRows(result));
+
+V[d] = result;
+@@

instructionAPI/ISA_ps/aesimc_advsimd

@@ -0,0 +1,12 @@
+##aesimc_advsimd_execute
+CheckCryptoEnabled64();
+
+bits(128) operand = V[n];
+bits(128) result;
+if decrypt then
+    result = AESInvMixColumns(operand);
+else
+    result = AESMixColumns(operand);
+end
+V[d] = result;
+@@

instructionAPI/ISA_ps/aesmc_advsimd

@@ -0,0 +1,12 @@
+##aesmc_advsimd_execute
+CheckCryptoEnabled64();
+
+bits(128) operand = V[n];
+bits(128) result;
+if decrypt then
+    result = AESInvMixColumns(operand);
+else
+    result = AESMixColumns(operand);
+end
+V[d] = result;
+@@

instructionAPI/ISA_ps/and_advsimd

@@ -0,0 +1,18 @@
+##and_advsimd_execute
+CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+if invert then operand2 = NOT(operand2);
+
+case op of
+    when LogicalOp_AND
+        result = operand1 AND operand2;
+    end
+    when LogicalOp_ORR
+        result = operand1 OR operand2;
+    end
+
+V[d] = result;
+@@