Add dyninstAPI/src/codegen-x86.C

dyninst · Apr 3, 2024 · f2ca692 · f2ca692
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Showing 2 changed files with 35 additions and 30 deletions.
diff --git a/docs/dyninstAPI/developer/codegen-x86.h.rst b/docs/dyninstAPI/developer/codegen-x86.h.rst
@@ -1,4 +1,4 @@
-.. _`sec:codegen-x86.h`:
+.. _`sec-dev:codegen-x86.h`:
 
 codegen-x86.h
 #############
@@ -12,11 +12,13 @@ codegen-x86.h
 
   .. cpp:function:: static void generatePush64(codeGen &gen, Dyninst::Address val)
 
-    More code generation
+    Unified the 64-bit push between branch and call
 
   .. cpp:function:: static void generateBranch(codeGen &gen, Dyninst::Address from, Dyninst::Address to)
 
-    Code generation
+    Change the insn at ``addr`` to be a branch to ``newAddr``.
+
+    Used to add multiple tramps to a point.
 
   .. cpp:function:: static void generateBranch(codeGen &gen, int disp)
   .. cpp:function:: static void generateBranch64(codeGen &gen, Dyninst::Address to)
@@ -29,14 +31,41 @@ codegen-x86.h
   .. cpp:function:: static void generateIllegal(codeGen &gen)
   .. cpp:function:: static void generateTrap(codeGen &gen)
   .. cpp:function:: static void generate(codeGen &gen, instruction &insn)
-  .. cpp:function:: static bool generate(codeGen &gen, instruction &insn, AddressSpace *addrSpace, Dyninst::Address origAddr, Dyninst::Address newAddr, patchTarget *fallthroughOverride = NULL, patchTarget *targetOverride = NULL)
+  .. cpp:function:: static bool generate(codeGen &gen, instruction &insn, AddressSpace *addrSpace, Dyninst::Address origAddr,\
+                                         Dyninst::Address newAddr, patchTarget *fallthroughOverride = NULL,\
+                                         patchTarget *targetOverride = NULL)
 
     And generate an equivalent stream somewhere else... fallthroughOverride and targetOverride are
     used for making the behavior of jumps change. It won't work for jumptables that should be cleared up sometime.
 
-  .. cpp:function:: static bool generateMem(codeGen &gen, instruction &insn, Dyninst::Address origAddr, Dyninst::Address newAddr, Dyninst::Register newLoadReg, Dyninst::Register newStoreReg)
+  .. cpp:function:: static bool generateMem(codeGen &gen, instruction &insn, Dyninst::Address origAddr, Dyninst::Address newAddr,\
+                                            Dyninst::Register newLoadReg, Dyninst::Register newStoreReg)
+
+    The comments and naming schemes in this function assume some familiarity with the IA32/IA32e
+    instruction encoding.  If you don't understand this, I suggest you start with Chapter 2 of IA-32
+    Intel Architecture Software Developer's Manual, Volume 2a and appendix A of: IA-32 Intel
+    Architecture Software Developer's Manual, Volume 2b.
+
+    This function takes an instruction
+    that accesses memory, and emits a  copy of that instruction that has the load/store replaces with a
+    load/store through a register.  For example, if this function were called with 'loadExpr = r12' on
+    the instruction 'mov 12(%rax)->%rbx', we would emit 'mov (%r12)->%rbx'. Note that we strip off any
+    displacements, indexs, etc...  The register is assumed to contain the final address that will be
+    loaded/stored.
+
   .. cpp:function:: static bool modifyJump(Dyninst::Address target, NS_x86::instruction &insn, codeGen &gen)
   .. cpp:function:: static bool modifyJcc(Dyninst::Address target, NS_x86::instruction &insn, codeGen &gen)
   .. cpp:function:: static bool modifyCall(Dyninst::Address target, NS_x86::instruction &insn, codeGen &gen)
   .. cpp:function:: static bool modifyData(Dyninst::Address target, NS_x86::instruction &insn, codeGen &gen)
-  .. cpp:function:: static bool modifyDisp(signed long newDisp, NS_x86::instruction &insn, codeGen &gen, Dyninst::Architecture arch, Dyninst::Address addr)
+  .. cpp:function:: static bool modifyDisp(signed long newDisp, NS_x86::instruction &insn, codeGen &gen,\
+                                           Dyninst::Architecture arch, Dyninst::Address addr)
+
+
+.. cpp:function:: unsigned copy_prefixes_nosize(const unsigned char *&origInsn, unsigned char *&newInsn, unsigned insnType)
+
+  Copy all prefixes but the Operand-Size and Dyninst::Address-Size prefixes (0x66 and 0x67)
+
+.. cpp:function:: unsigned copy_prefixes_nosize_or_segments(const unsigned char *&origInsn, unsigned char *&newInsn, unsigned insnType) 
+
+  Copy all prefixes but the Operand-Size and Dyninst::Address-Size prefixes (0x66 and 0x67)
+  Returns the number of bytes copied
diff --git a/dyninstAPI/src/codegen-x86.C b/dyninstAPI/src/codegen-x86.C
@@ -83,7 +83,6 @@ unsigned copy_prefixes(const unsigned char *&origInsn, unsigned char *&newInsn,
   return nPrefixes;
 }
 
-//Copy all prefixes but the Operand-Size and Dyninst::Address-Size prefixes (0x66 and 0x67)
 unsigned copy_prefixes_nosize(const unsigned char *&origInsn, unsigned char *&newInsn, 
                               unsigned insnType) 
 {
@@ -102,8 +101,6 @@ unsigned copy_prefixes_nosize(const unsigned char *&origInsn, unsigned char *&ne
     return retval;
 }
 
-//Copy all prefixes but the Operand-Size and Dyninst::Address-Size prefixes (0x66 and 0x67)
-// Returns the number of bytes copied
 unsigned copy_prefixes_nosize_or_segments(const unsigned char *&origInsn, unsigned char *&newInsn, 
                               unsigned insnType) 
 {
@@ -204,11 +201,6 @@ void insnCodeGen::generateTrap(codeGen &gen) {
     SET_PTR(insn, gen);
 }
 
-/*
- * change the insn at addr to be a branch to newAddr.
- *   Used to add multiple tramps to a point.
- */
-
 void insnCodeGen::generateBranch(codeGen &gen,
                                  Dyninst::Address fromAddr, Dyninst::Address toAddr)
 {
@@ -261,7 +253,6 @@ void insnCodeGen::generateBranch(codeGen &gen,
 }
 
 
-// Unified the 64-bit push between branch and call
 void insnCodeGen::generatePush64(codeGen &gen, Dyninst::Address val)
 {
   GET_PTR(insn, gen);
@@ -739,21 +730,6 @@ bool pcRelData::canPreApply()
 #define SIB_SET_REG(x, y) ((x) |= ((y) & 7))
 #define SIB_SET_INDEX(x, y) ((x) |= (((y) & 7) << 3))
 
-/**
- * The comments and naming schemes in this function assume some familiarity with
- * the IA32/IA32e instruction encoding.  If you don't understand this, I suggest
- * you start with Chapter 2 of:
- *  _IA-32 Intel Dyninst::Architecture Software Developer's Manual, Volume 2a_
- * and appendix A of:
- *  _IA-32 Intel Dyninst::Architecture Software Developer's Manual, Volume 2b_
- *
- * This function takes an instruction that accesses memory, and emits a 
- * copy of that instruction that has the load/store replaces with a load/store
- * through a register.  For example, if this function were called with 'loadExpr = r12'
- * on the instruction 'mov 12(%rax)->%rbx', we would emit 'mov (%r12)->%rbx'.
- * Note that we strip off any displacements, indexs, etc...  The register is assumed
- * to contain the final address that will be loaded/stored.
- **/
 bool insnCodeGen::generateMem(codeGen &gen,
                               instruction & insn,
                               Dyninst::Address /*origAddr*/,