Skip to content

Commit

Permalink
Merge checkpoint
Browse files Browse the repository at this point in the history
  • Loading branch information
@wrwilliams
wrwilliams committed Aug 22, 2017
2 parents b00c212 + 74cf2a7 commit f9a3e41
Show file tree
Hide file tree
Showing 694 changed files with 28,721 additions and 12,678 deletions.
3 changes: 2 additions & 1 deletion .gitignore
View file
Expand Up @@ -118,4 +118,5 @@ doxyfiles/*
*/Debug/
*/Release/
cotire/
.idea/*
.idea/*
boost/
Binary file added common/docs/decoding_diagram.png
View file
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
Binary file added common/docs/rose_structure.png
View file
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
71 changes: 70 additions & 1 deletion common/h/dyn_regs.h
View file
Expand Up @@ -107,6 +107,7 @@ namespace Dyninst
bool isSyscallNumberReg() const;
bool isSyscallReturnValueReg() const;
bool isFlag() const;
bool isZeroFlag() const;

void getROSERegister(int &c, int &n, int &p);

Expand Down Expand Up @@ -889,6 +890,40 @@ namespace Dyninst
DEF_REGISTER(cr, 629 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(or3, 630 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(trap, 631 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr0l, 700 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr0g, 701 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr0e, 702 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr0s, 703 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr1l, 704 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr1g, 705 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr1e, 706 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr1s, 707 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr2l, 708 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr2g, 709 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr2e, 710 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr2s, 711 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr3l, 712 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr3g, 713 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr3e, 714 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr3s, 715 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr4l, 716 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr4g, 717 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr4e, 718 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr4s, 719 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr5l, 720 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr5g, 721 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr5e, 722 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr5s, 723 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr6l, 724 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr6g, 725 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr6e, 726 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr6s, 727 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr7l, 728 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr7g, 729 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr7e, 730 | SPR | Arch_ppc32, "ppc32");
DEF_REGISTER(cr7s, 731 | SPR | Arch_ppc32, "ppc32");


}
namespace ppc64 {
const signed int GPR = 0x00010000;
Expand Down Expand Up @@ -1070,6 +1105,40 @@ namespace Dyninst
DEF_REGISTER(cr, 629 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(or3, 630 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(trap, 631 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr0l, 700 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr0g, 701 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr0e, 702 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr0s, 703 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr1l, 704 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr1g, 705 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr1e, 706 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr1s, 707 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr2l, 708 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr2g, 709 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr2e, 710 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr2s, 711 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr3l, 712 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr3g, 713 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr3e, 714 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr3s, 715 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr4l, 716 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr4g, 717 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr4e, 718 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr4s, 719 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr5l, 720 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr5g, 721 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr5e, 722 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr5s, 723 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr6l, 724 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr6g, 725 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr6e, 726 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr6s, 727 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr7l, 728 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr7g, 729 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr7e, 730 | SPR | Arch_ppc64, "ppc64");
DEF_REGISTER(cr7s, 731 | SPR | Arch_ppc64, "ppc64");


}

namespace aarch64{
Expand Down Expand Up @@ -1380,11 +1449,11 @@ namespace Dyninst
DEF_REGISTER(wsp, 0 | D_REG |SPR | Arch_aarch64, "aarch64");
DEF_REGISTER(pc, 1 | FULL |SPR | Arch_aarch64, "aarch64");
DEF_REGISTER(pstate, 2 | D_REG |SPR | Arch_aarch64, "aarch64");
DEF_REGISTER(xzr, 3 | FULL |SPR | Arch_aarch64, "aarch64");
DEF_REGISTER(n, N_FLAG | BIT |FLAG| Arch_aarch64, "aarch64");
DEF_REGISTER(z, Z_FLAG | BIT |FLAG| Arch_aarch64, "aarch64");
DEF_REGISTER(c, C_FLAG | BIT |FLAG| Arch_aarch64, "aarch64");
DEF_REGISTER(v, V_FLAG | BIT |FLAG| Arch_aarch64, "aarch64");
DEF_REGISTER(zr, 3 | FULL |SPR | Arch_aarch64, "aarch64");
DEF_REGISTER(wzr, 3 | D_REG |SPR | Arch_aarch64, "aarch64");
DEF_REGISTER(fpcr, 4 | D_REG |SPR | Arch_aarch64, "aarch64");
DEF_REGISTER(fpsr, 5 | D_REG |SPR | Arch_aarch64, "aarch64");
Expand Down
30 changes: 30 additions & 0 deletions common/h/entryIDs.h
View file
Expand Up @@ -35,14 +35,19 @@

enum entryID {
e_jb = 0,
e_ja,
e_jb_jnaej_j,
e_jbe,
e_jge,
e_jcxz_jec,
e_jl,
e_jle,
e_jmp,
e_jmpq,
e_jmpe,
e_je,
e_jnb,
e_jne,
e_jnb_jae_j,
e_jnbe,
e_jnl,
Expand All @@ -55,11 +60,17 @@ enum entryID {
e_jp,
e_js,
e_jz,
e_jg,
e_jrcxz,
e_loop,
e_loope,
e_loopn,
e_loopne,
e_call,
e_callq,
e_cmp,
e_cmpw,
e_cmpsl,
e_cmppd,
e_cmpps,
e_cmpsb,
Expand Down Expand Up @@ -161,6 +172,7 @@ enum entryID {
e_cvttss2si,
e_cwd,
e_cwde,
e_cwtl,
e_aesenc,
e_aesenclast,
e_aesdec,
Expand All @@ -178,6 +190,7 @@ enum entryID {
e_daa,
e_das,
e_dec,
e_decl,
e_div,
e_divpd,
e_divps,
Expand All @@ -188,6 +201,7 @@ enum entryID {
e_dpps, // SSE 4.1
e_emms,
e_enter,
e_enterq,
e_extractps, // SSE 4.1
e_extrq,
e_fadd,
Expand All @@ -208,6 +222,7 @@ enum entryID {
e_fcomi,
e_fcomip,
e_fcomp,
e_fcomps,
e_fcompp,
e_fdiv,
e_fdivp,
Expand Down Expand Up @@ -235,17 +250,20 @@ enum entryID {
e_fmul,
e_fmulp,
e_fnop,
e_fnstcw,
e_fprem,
e_frstor,
e_fsave,
e_xbegin,
e_xabort,
e_xrstors,
e_fst,
e_fstcw,
e_fstenv,
e_fstp,
e_fstsw,
e_fsub,
e_fsubl,
e_fsubp,
e_fsubr,
e_fsubrp,
Expand Down Expand Up @@ -286,6 +304,7 @@ enum entryID {
e_lds,
e_lea,
e_leave,
e_leaveq,
e_les,
e_lfence,
e_lfs,
Expand All @@ -294,6 +313,7 @@ enum entryID {
e_lidt,
e_lldt,
e_lmsw,
e_lods,
e_lodsb,
e_lodsd,
e_lodsw,
Expand All @@ -313,6 +333,8 @@ enum entryID {
e_minss,
e_mmxud,
e_mov,
e_movsl,
e_movabs,
e_movapd,
e_movaps,
e_movd,
Expand Down Expand Up @@ -452,6 +474,7 @@ enum entryID {
e_popa,
e_popad,
e_popf,
e_popfq,
e_popfd,
e_popcnt,
e_por,
Expand Down Expand Up @@ -505,6 +528,7 @@ enum entryID {
e_rdtsc,
e_rdrand,
e_rol,
e_rolb,
e_ror,
e_roundpd, // SSE 4.1
e_roundps, // SSE 4.1
Expand All @@ -516,7 +540,10 @@ enum entryID {
e_sahf,
e_salc,
e_sar,
e_sarb,
e_sbb,
e_sbbl,
e_scas,
e_scasb,
e_scasd,
e_scasw,
Expand All @@ -541,6 +568,7 @@ enum entryID {
e_shl_sal,
e_shld,
e_shr,
e_shrb,
e_shrd,
e_shufpd,
e_shufps,
Expand All @@ -566,6 +594,7 @@ enum entryID {
e_std,
e_sti,
e_stmxcsr,
e_stos,
e_stosb,
e_stosd,
e_stosw,
Expand Down Expand Up @@ -612,6 +641,7 @@ enum entryID {
e_vblendvps,
e_vblendvpd,
e_vpblendmw,
e_vpblendmd,
e_vpblendmb,
e_vpblendvb,
e_vcmppd,
Expand Down

0 comments on commit f9a3e41

Please sign in to comment.