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[ARM Decoding] SQSHL instruction has invalid bits set #235

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nathanhjay opened this issue Nov 15, 2016 · 1 comment
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[ARM Decoding] SQSHL instruction has invalid bits set #235

nathanhjay opened this issue Nov 15, 2016 · 1 comment
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ARM decoding cleanup

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@nathanhjay
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This instruction should be invalid.

Bytes: 03 7f b6 5f
Output: sqshl q3, q24
@wrwilliams wrwilliams added the bug label Feb 9, 2017
@wrwilliams wrwilliams modified the milestone: ARM decoding cleanup Mar 14, 2017
ssunny7 added a commit that referenced this issue May 2, 2017
@ssunny7
Issues #235(SQSHL instruction has invalid bits set ) and #236(Compare…
1eff200 
… instructions with zero ignore reserved bits)

Added a new method to perform a check on invalid bits for certain instructions before processing their operands.
@ssunny7
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ssunny7 commented May 2, 2017

Fixed by 1eff200.

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@sashanicolas @wrwilliams @nathanhjay @ssunny7