Merge arm64/feature/semantics_setup into master #127
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…ruction objects for ARMv8 This commit is the first in a branch that will contain all changes for enabling the conversion from ARMv8 Instruction API objects to SgAsmInstruction objects. Since ROSE doesn't support ARMv8, the instruction representation for it has been added by extending SgAsmInstruction. getROSERegister is also modified to map Dyninst registers to ROSE ARMv8 registers, which have again been newly added and are defined in the armv8InstructionEnum file. ROSE instruction factory for ARMv8 does not perform any processing to Instruction API operands when performing the conversion (unlike x86 and Power) -- this is primarily because there is no existing ARMv8 semantics to conform to. This commit also brings in lots of changes to the ROSE interface for representing an instruction and its parts: * SgAsm*ValueExpression types are now replaces with SgAsm(Integer/Float)ValueExpression types; SgAsmType* have been replaced by SgAsmType(Integer/Float). The old classes remain to support the existing x86/Power semantics. * Several changes are made to the classes that were already present. These changes support existing semantics and will also work for ARMv8. * New classes have been added for representation of expressions. * Several classes in the Sawyer namespace of ROSE have been added -- these are used in the newly introduced Sg* classes, and will also be used for ARM semantics. * ROSE's new representation for registers uses RegisterDescriptor and a new class for register expressions (SgAsmDirectRegisterExoression). * The new types are used based on a check on the architecture. * Opcodes for ARMv8 have the same name in ROSE as in Dyninst, except that the name is prefixed by the string "rose_".
This commit brings in and sets up all the files required to use the new ROSE semantics framework from within Dyninst. The starting point for this was the src/midend/binaryAnalyses/instructionSemantics folder within ROSE's source tree. All the other files have been added because semantics directlyu or indirectly depends on them. After adding the file to the Dyninst source, several changes may or may not have been made to it. Most of the changes revolve around updating the include paths and removing any macros used by ROSE but not required by Dyninst. Other minor changes have also been made based on build errors/warnings. Currently, he build succeeds but with a ton of warnings. I've suppressed them for the time being. By doing this, both old and new instruction semantics should ideally be able to co-exist, although this hasn't been tested yet.
Before the dispatcher for ARM64 can be called for instruction processing, the value type, register state, memory state and RISC operators need to be initialized. Ideally, these should be specific to Dyninst's SymEvalPolicy. That policy, however, needs to be re-written to work with the new semantics - this hasn't been done yet. Thus the current initializations of the type, states and operators use the base types (defined in BaseSemantics2.h) and will later by replaced by concretized versions.
SymEvalPolicy is now called "SymEvalSemantics" - in line with the terminology of the new semantics framework. Using this requires the implementation of 4 main classes - SValue (the value type), RegisterState, MemoryState and RiscOperators. All of these inherit from their respective definitions in BaseSemantics2.h. Everything from the old policy (eg. SymEvalPolicy) needs to be mapped to these 4 classes. Currently, the implementation of SValue is mostly complete (a couple methods are yet to be implemented and few others need a little more thought) and declarations for some methods in RiscOperators have been added.
…mEval semantics are now complete. Also modified the intialization of all 4 required components in SymEval.C to use the new definitions instead of those in BaseSemantics2.h. The final RiscOperators object is thus setup to be usable by Dyninst.
…iscOperators class. Most of these micro-operations just translate to the creation of a unary/binary/ternary AST. Utility methods for creating such ASTs and then wrapping them around a SValuePtr are also added.
…perators class for use by SymEvalSemantics.
…ARM64 for use by wrap(). When calling wrap() in RegisterStateARM64::readRegister(), the Dyninst::Address member passed in to StateARM64 needs to be accessed. A new RegisterStateARM64::readRegister is added which takes the RegisterDescriptor and the Dyninst::Address, and the default readRegister() causes an assert(). RiscOperators in SymEvalSemantics is renamed to RiscOperatorsARM64. Two methods in it were wrongly named -- they have been renamed to their correct versions. Building of SymEvalSemantics is also enabled now.
…ocessing A BaseSemantics::Dispatcher object is created using the passed in RiscOperators object during the expansion of ARM64 instructions. A similar thing will be done for other architectures once they move to the new semantics.
* Direct register expressions need to have their type set - this is set to SgAsmIntegerType for now. The type's signed-ness is set to unsigned, but it shouldn't matter because the only place register expressions' types are used is when accessing the width. * regPos wasn't being set correctly for ARM flags when converting a Dyninst register to a ROSE register. * The correct jump table analysis functions are now being called for ARM binaries.
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This merge brings into Dyninst support for the new ROSE semantics framework. Future branches related to this topic should either be made for adding support for more instructions' semantics or for bug fixes.