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Clean up and improve documentation of x86_64 registers #1630

Merged
merged 39 commits into from
Nov 21, 2023
Merged

Clean up and improve documentation of x86_64 registers #1630

merged 39 commits into from
Nov 21, 2023

Commits on Nov 21, 2023

  1. Improve comments for register lengths

    @hainest
    hainest committed Nov 21, 2023
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  2. Separate MMX/3DNow! and x87 register lengths 

    The MMX* registers are only the lower 64 bits of the st* ones.
    @hainest
    hainest committed Nov 21, 2023
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  3. Fix x86_64 subrange mappings in MachRegister::getROSERegister 

    The values in the two namespaces are not the same.
    @hainest
    hainest committed Nov 21, 2023
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  4. Clean up size calculation in MachRegister

    @hainest
    hainest committed Nov 21, 2023
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  5. Separate MMX/3DNow! and x87 register categories

    @hainest
    hainest committed Nov 21, 2023
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  6. Reorder the length flags 

    This puts them in more of a chronological order.
    @hainest
    hainest committed Nov 21, 2023
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  7. Improve comments for register categories

    @hainest
    hainest committed Nov 21, 2023
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  8. Reorder register categories 

    This puts them in more of a chronological order.
    @hainest
    hainest committed Nov 21, 2023
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  9. Move FLAGS ID down with the others.

    @hainest
    hainest committed Nov 21, 2023
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  10. Add comments for aliased GPRs 

    No real comments here. Just added a separator.
    @hainest
    hainest committed Nov 21, 2023
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  11. Improve comments for EFLAGS fields

    @hainest
    hainest committed Nov 21, 2023
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  12. Move FLAGS ID

    @hainest
    hainest committed Nov 21, 2023
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  13. Use symbolic names for the segment register base IDs

    @hainest
    hainest committed Nov 21, 2023
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  14. Add missing flag1 from RFLAGS

    @hainest
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  15. Add missing flag3 from RFLAGS

    @hainest
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  16. Add missing flag5 from RFLAGS

    @hainest
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  17. Add missing flagc from RFLAGS 

    FLAGC is the lower bit of the I/O Permission Level field.
    @hainest
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  18. Add missing flagd from RFLAGS 

    FLAGC is the upper bit of the I/O Permission Level field.
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  19. Add missing flagf from RFLAGS

    @hainest
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  20. Improve comments about RFLAGS

    @hainest
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  21. Add missing Virtual-8086 mode (VM) rFLAGS field

    @hainest
    hainest committed Nov 21, 2023
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  22. Add conversion to ROSE register for Resume Flag

    @hainest
    hainest committed Nov 21, 2023
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  23. Add conversion to ROSE register for Nested Task flag

    @hainest
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  24. Add missing Alignment Check/Access Control (AC) RFLAGS field

    @hainest
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  25. Add missing Virtual Interrupt Flag (VIF) RFLAGS field

    @hainest
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  26. Add missing Virtual Interrupt Pending (VIP) RFLAGS field

    @hainest
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  27. Add missing ID Flag (ID) RFLAGS field

    @hainest
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  28. Improve descriptions in comment about format of constants

    @hainest
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  29. Fix avx-512 opmask size. 

    It's 64 bits, not 128.

From Intel(R) 64 and IA-32 Architectures Software Developer’s Manual
June 2021

15.6.1 OPMASK Register to Predicate Vector Data Processing
  The opmask is a set of eight architectural registers of size
  MAX_KL (64-bit).
    @hainest
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  30. Rename OCT to XMMS 

    This makes it consistent with the names used for the other vector
extensions.
    @hainest
    hainest committed Nov 21, 2023
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  31. Reorder register declarations 

    It makes it easier to read.
    @hainest
    hainest committed Nov 21, 2023
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  32. Add missing subranges in MachRegister::getROSERegister

    @hainest
    hainest committed Nov 21, 2023
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  33. Use st0 as base register for MMX

    @hainest
    hainest committed Nov 21, 2023
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  34. Use ymm0 as base register for SSE

    @hainest
    hainest committed Nov 21, 2023
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  35. Use zmm0 as base register for AVX

    @hainest
    hainest committed Nov 21, 2023
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  36. Fix comment on XMM, YMM, ZMM register numbers 

    Assume AMD64 extensions are in place so that XMM8-XMM15 are
present.
    @hainest
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  37. Preserve register number in getBaseRegister

    @hainest
    hainest committed Nov 21, 2023
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  38. Clear whole subrange byte for GPRs in getBaseRegister

    @hainest
    hainest committed Nov 21, 2023
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  39. Synchronize values for VM...ID with x86

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