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Update VM code & setting for RISC-V in OpenJ9 (part6/VM) #7445
Update VM code & setting for RISC-V in OpenJ9 (part6/VM) #7445
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Already verified the compilation on Fedora_Linux/QEMU. Note: The JIT related code (on register setting) util/jitregs.c was written against the RISC-V Spec (please refer to https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf for details) In addition, rv64helpers.m4 & rv64cinterp.m4 should be updated by JIT later to insert JIT frames so Reviewer: @keithc-ca, @gacholio, @pshipton , @DanHeidinga |
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@ChengJin01 Please resolve the merge conficts. |
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@keithc-ca, the conflict has been fixed. |
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@keithc-ca & @gacholio , I updated the code with |
The jvminit merge seems correct to me. |
Agreed, bytecodeLoop updates look good! |
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@gacholio Please add your approval if you're satisfied with this. |
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jenkins test sanity zlinux jdk8 |
jenkins test sanity plinux jdk8 |
The changes mainly update & add interpreter specific code (with placeholders to be replaced by JIT) & setting to enable on RISC-V 64bit from the OpenJ9 perspective. Issue: eclipse#7421 Signed-off-by: Cheng Jin <jincheng@ca.ibm.com>
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I saw enough testing pass to prove there's no cross-platform issues, and the latest push was an obvious fix in a file only compiled on the new processor, so I'm merging this. |
The changes mainly update & add interpreter specific code
(with placeholders to be replaced by JIT) & setting
to enable on RISC-V 64bit from the OpenJ9 perspective.
Issue: eclipse#7421
Signed-off-by: Cheng Jin jincheng@ca.ibm.com