Merge pull request #6499 from janvrany/pr/riscv-add-CPU-class

RISC-V: add CPU class
eclipse · Jun 17, 2022 · 14031e5 · 14031e5
2 parents 5166bf0 + 9cf62a8
commit 14031e5
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diff --git a/compiler/riscv/CMakeLists.txt b/compiler/riscv/CMakeLists.txt
@@ -1,5 +1,5 @@
 #################################################################################
-# Copyright (c) 2019, 2021 IBM Corp. and others
+# Copyright (c) 2019, 2022 IBM Corp. and others
 #
 # This program and the accompanying materials are made available under
 # the terms of the Eclipse Public License 2.0 which accompanies this
@@ -42,5 +42,6 @@ compiler_library(riscv
 	${CMAKE_CURRENT_LIST_DIR}/codegen/UnaryEvaluator.cpp
 	${CMAKE_CURRENT_LIST_DIR}/codegen/RVHelperCallSnippet.cpp
 	${CMAKE_CURRENT_LIST_DIR}/env/OMRDebugEnv.cpp
+	${CMAKE_CURRENT_LIST_DIR}/env/OMRCPU.cpp
 	${CMAKE_CURRENT_LIST_DIR}/runtime/CodeSync.cpp
 )
diff --git a/compiler/riscv/env/OMRCPU.cpp b/compiler/riscv/env/OMRCPU.cpp
@@ -0,0 +1,61 @@
+/*******************************************************************************
+ * Copyright (c) 2022, 2022 IBM Corp. and others
+ *
+ * This program and the accompanying materials are made available under
+ * the terms of the Eclipse Public License 2.0 which accompanies this
+ * distribution and is available at http://eclipse.org/legal/epl-2.0
+ * or the Apache License, Version 2.0 which accompanies this distribution
+ * and is available at https://www.apache.org/licenses/LICENSE-2.0.
+ *
+ * This Source Code may also be made available under the following Secondary
+ * Licenses when the conditions for such availability set forth in the
+ * Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
+ * version 2 with the GNU Classpath Exception [1] and GNU General Public
+ * License, version 2 with the OpenJDK Assembly Exception [2].
+ *
+ * [1] https://www.gnu.org/software/classpath/license.html
+ * [2] http://openjdk.java.net/legal/assembly-exception.html
+ *
+ * SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
+ *******************************************************************************/
+
+#include "env/CPU.hpp"
+#include "env/CompilerEnv.hpp"
+#include "env/jittypes.h"
+#include "omrport.h"
+
+bool
+OMR::RV::CPU::isTargetWithinUnconditionalBranchImmediateRange(intptr_t targetAddress, intptr_t sourceAddress)
+   {
+   intptr_t range = targetAddress - sourceAddress;
+   return range <= self()->maxUnconditionalBranchImmediateForwardOffset() &&
+          range >= self()->maxUnconditionalBranchImmediateBackwardOffset();
+   }
+
+bool
+OMR::RV::CPU::supportsFeature(uint32_t feature)
+   {
+   if (TR::Compiler->omrPortLib == NULL)
+      {
+      return false;
+      }
+
+   OMRPORT_ACCESS_FROM_OMRPORT(TR::Compiler->omrPortLib);
+   return (TRUE == omrsysinfo_processor_has_feature(&_processorDescription, feature));
+   }
+
+const char*
+OMR::RV::CPU::getProcessorName()
+   {
+   const char* returnString = "";
+   switch(_processorDescription.processor)
+      {
+      case OMR_PROCESOR_RISCV64_UNKNOWN:
+         returnString = "Unknown RV64G processor";
+         break;
+      default:
+         returnString = "Unknown RISC-V processor";
+         break;
+      }
+   return returnString;
+   }
diff --git a/compiler/riscv/env/OMRCPU.hpp b/compiler/riscv/env/OMRCPU.hpp
@@ -0,0 +1,138 @@
+/*******************************************************************************
+ * Copyright (c) 2022, 2022 IBM Corp. and others
+ *
+ * This program and the accompanying materials are made available under
+ * the terms of the Eclipse Public License 2.0 which accompanies this
+ * distribution and is available at http://eclipse.org/legal/epl-2.0
+ * or the Apache License, Version 2.0 which accompanies this distribution
+ * and is available at https://www.apache.org/licenses/LICENSE-2.0.
+ *
+ * This Source Code may also be made available under the following Secondary
+ * Licenses when the conditions for such availability set forth in the
+ * Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
+ * version 2 with the GNU Classpath Exception [1] and GNU General Public
+ * License, version 2 with the OpenJDK Assembly Exception [2].
+ *
+ * [1] https://www.gnu.org/software/classpath/license.html
+ * [2] http://openjdk.java.net/legal/assembly-exception.html
+ *
+ * SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
+ *******************************************************************************/
+
+#ifndef OMR_RV_CPU_INCL
+#define OMR_RV_CPU_INCL
+
+/*
+ * The following #define and typedef must appear before any #includes in this file
+ */
+#ifndef OMR_CPU_CONNECTOR
+#define OMR_CPU_CONNECTOR
+namespace OMR { namespace RV { class CPU; } }
+namespace OMR { typedef OMR::RV::CPU CPUConnector; }
+#else
+#error OMR::RV::CPU expected to be a primary connector, but an OMR connector is already defined
+#endif
+
+#include <stdint.h>
+#include "compiler/env/OMRCPU.hpp"
+#include "env/jittypes.h"
+
+
+namespace OMR
+{
+
+namespace RV
+{
+
+class OMR_EXTENSIBLE CPU : public OMR::CPU
+   {
+protected:
+
+   CPU() : OMR::CPU()
+      {
+      _processorDescription.processor = OMR_PROCESOR_RISCV64_UNKNOWN;
+      _processorDescription.physicalProcessor = OMR_PROCESOR_RISCV64_UNKNOWN;
+      memset(_processorDescription.features, 0, OMRPORT_SYSINFO_FEATURES_SIZE*sizeof(uint32_t));
+      }
+   CPU(const OMRProcessorDesc& processorDescription) : OMR::CPU(processorDescription) {}
+
+public:
+
+   /**
+    * @brief Answers whether the CPU has hardware support for SQRT or not
+    * @return true if supported, false otherwise
+    */
+   bool getSupportsHardwareSQRT() { return false; }
+
+   /**
+    * @brief Provides the maximum forward branch displacement in bytes reachable
+    *        with a relative unconditional branch with immediate (B or BL) instruction.
+    *
+    * @return Maximum forward branch displacement in bytes.
+    */
+   int32_t maxUnconditionalBranchImmediateForwardOffset() { return 0x7FFFF; }
+
+   /**
+    * @brief Provides the maximum backward branch displacement in bytes reachable
+    *        with a relative unconditional branch with immediate (B or BL) instruction.
+    *
+    * @return Maximum backward branch displacement in bytes.
+    */
+   int32_t maxUnconditionalBranchImmediateBackwardOffset() { return 0xFFF80000; }
+
+   /**
+    * @brief Answers whether the distance between a target and source address
+    *        is within the reachable displacement range for a relative unconditional
+    *        branch with immediate (B or BL) instruction.
+    *
+    * @param[in] : targetAddress : the address of the target
+    *
+    * @param[in] : sourceAddress : the address of the relative unconditional branch
+    *                 with immediate (B or BL) instruction from which the
+    *                 displacement range is measured.
+    *
+    * @return true if the target is within range; false otherwise.
+    */
+   bool isTargetWithinUnconditionalBranchImmediateRange(intptr_t targetAddress, intptr_t sourceAddress);
+
+   /**
+    * @brief Determines whether 32bit integer rotate is available
+    *
+    * @details
+    *    Returns true if 32bit integer rotate to left is available when requireRotateToLeft is true.
+    *    Returns true if 32bit integer rotate (right or left) is available when requireRotateToLeft is false.
+    *
+    * @param requireRotateToLeft if true, returns true if rotate to left operation is available.
+    */
+   bool getSupportsHardware32bitRotate(bool requireRotateToLeft=false) { return false; } // no rotate in RV64G
+   /**
+    * @brief Determines whether 64bit integer rotate is available
+    *
+    * @details
+    *    Returns true if 64bit integer rotate to left is available when requireRotateToLeft is true.
+    *    Returns true if 64bit integer rotate (right or left) is available when requireRotateToLeft is false.
+    *
+    * @param requireRotateToLeft if true, returns true if rotate to left operation is available.
+    */
+   bool getSupportsHardware64bitRotate(bool requireRotateToLeft=false) { return false; } // no rotate in RV64G
+
+   /**
+    * @brief Answers if the specified feature is supported by this cpu
+    *
+    * @param[in] feature: feature bit
+    * @returns true if feature is supported
+    */
+   bool supportsFeature(uint32_t feature);
+
+   /**
+    * @brief Returns name of the current processor
+    * @returns const char* string representing the name of the current processor
+    */
+   const char* getProcessorName();
+   };
+
+}
+
+}
+
+#endif