Use common assocreg instruction on x86

eclipse · Jun 9, 2021 · 2200a36 · 2200a36
1 parent 1fb5ba9
commit 2200a36
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Showing 6 changed files with 8 additions and 14 deletions.
diff --git a/compiler/x/codegen/OMRInstOpCode.enum b/compiler/x/codegen/OMRInstOpCode.enum
@@ -1046,7 +1046,6 @@
    DWImm2,
    DBImm1,
    WRTBAR,
-   ASSOCREGS,
    FPREGSPILL,
    VirtualGuardNOP,
    LABEL,

diff --git a/compiler/x/codegen/OMRInstOpCode.enum.temp.defines b/compiler/x/codegen/OMRInstOpCode.enum.temp.defines
@@ -1034,7 +1034,6 @@
 #define   DWImm2 OMR::InstOpCode::DWImm2
 #define   DBImm1 OMR::InstOpCode::DBImm1
 #define   WRTBAR OMR::InstOpCode::WRTBAR
-#define   ASSOCREGS OMR::InstOpCode::ASSOCREGS
 #define   FPREGSPILL OMR::InstOpCode::FPREGSPILL
 #define   VirtualGuardNOP OMR::InstOpCode::VirtualGuardNOP
 #define   LABEL OMR::InstOpCode::LABEL

diff --git a/compiler/x/codegen/OMRInstruction.cpp b/compiler/x/codegen/OMRInstruction.cpp
@@ -69,7 +69,7 @@ OMR::X86::Instruction::initialize(TR::CodeGenerator *cg, TR::RegisterDependencyC
    self()->assumeValidInstruction();
    self()->clobberRegsForRematerialisation();
 
-   if (cond && op != ASSOCREGS)
+   if (cond && op != TR::InstOpCode::assocreg)
       {
       cond->useRegisters(self(), cg);
 
@@ -126,7 +126,7 @@ void OMR::X86::Instruction::assignRegisters(TR_RegisterKinds kindsToBeAssigned)
       return;
       }
 
-   if (self()->getOpCodeValue() != ASSOCREGS)
+   if (self()->getOpCodeValue() != TR::InstOpCode::assocreg)
       {
       if ((self()->cg()->getAssignmentDirection() == self()->cg()->Backward))
          {
@@ -139,7 +139,7 @@ void OMR::X86::Instruction::assignRegisters(TR_RegisterKinds kindsToBeAssigned)
          self()->getDependencyConditions()->assignPostConditionRegisters(self(), kindsToBeAssigned, self()->cg());
          }
       }
-   else if ((self()->getOpCodeValue() == ASSOCREGS) && self()->cg()->enableRegisterAssociations())
+   else if ((self()->getOpCodeValue() == TR::InstOpCode::assocreg) && self()->cg()->enableRegisterAssociations())
       {
       if (kindsToBeAssigned & TR_GPR_Mask)
          {
@@ -255,7 +255,7 @@ void OMR::X86::Instruction::clobberRegsForRematerialisation()
    //
    if (  self()->cg()->enableRematerialisation()
       && self()->getDependencyConditions()
-      && (self()->getOpCodeValue() != ASSOCREGS)  // reg associations aren't really instructions, so they don't modify anything
+      && (self()->getOpCodeValue() != TR::InstOpCode::assocreg)  // reg associations aren't really instructions, so they don't modify anything
       && (self()->getOpCodeValue() != LABEL)      // labels must already be handled properly for a variety of reasons
       && (!self()->getOpCode().isShiftOp())
       && (!self()->getOpCode().isRotateOp())      // shifts and rotates often have a postcondition on ecx but don't clobber it

diff --git a/compiler/x/codegen/OMRMachine.cpp b/compiler/x/codegen/OMRMachine.cpp
@@ -396,7 +396,7 @@ OMR::X86::Machine::findBestFreeGPRegister(TR::Instruction   *currentInstruction,
          if (cursor->getOpCodeValue() == PROCENTRY)
             break;
 
-         if (cursor->getOpCodeValue() == ASSOCREGS)
+         if (cursor->getOpCodeValue() == TR::InstOpCode::assocreg)
             continue;
 
          for (i = 0; i < numCandidates; i++)
@@ -1532,11 +1532,11 @@ OMR::X86::Machine::createRegisterAssociationDirective(TR::Instruction *cursor)
 
    associations->stopAddingPostConditions();
 
-   new (self()->cg()->trHeapMemory()) TR::Instruction(associations, ASSOCREGS, cursor, self()->cg());
+   new (self()->cg()->trHeapMemory()) TR::Instruction(associations, TR::InstOpCode::assocreg, cursor, self()->cg());
    if (cursor == self()->cg()->getAppendInstruction())
       self()->cg()->setAppendInstruction(cursor->getNext());
 
-   // There's no need to have a virtual appear in more than one ASSOCREGS after
+   // There's no need to have a virtual appear in more than one TR::InstOpCode::assocreg after
    // its live range has ended.  One is enough.  So we clear out all the dead
    // registers from the associations.
    //

diff --git a/compiler/x/codegen/OMRTreeEvaluator.cpp b/compiler/x/codegen/OMRTreeEvaluator.cpp
@@ -3504,7 +3504,7 @@ TR::Register *OMR::X86::TreeEvaluator::BBEndEvaluator(TR::Node *node, TR::CodeGe
       TR::Machine *machine = cg->machine();
 
       if (cg->enableRegisterAssociations() &&
-          cg->getAppendInstruction()->getOpCodeValue() != ASSOCREGS)
+          cg->getAppendInstruction()->getOpCodeValue() != TR::InstOpCode::assocreg)
          {
          machine->createRegisterAssociationDirective(cg->getAppendInstruction());
          }

diff --git a/compiler/x/codegen/X86Ops.ins b/compiler/x/codegen/X86Ops.ins
@@ -4120,10 +4120,6 @@ INSTRUCTION(WRTBAR, wrtbar, // Write barrier directive/macro for GCs that need t
             BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0x00, 0, ModRM_NONE, Immediate_0),
             PROPERTY0(IA32OpProp_UsesTarget | IA32OpProp_ModifiesTarget | IA32OpProp_IntSource | IA32OpProp_IntTarget | IA32OpProp_ByteTarget),
             PROPERTY1(IA32OpProp1_PseudoOp)),
-INSTRUCTION(ASSOCREGS, assocRegs, // Directive to change register associations
-            BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0x00, 0, ModRM_NONE, Immediate_0),
-            PROPERTY0(0),
-            PROPERTY1(IA32OpProp1_PseudoOp)),
 INSTRUCTION(FPREGSPILL, fpRegSpill, // Directive to force the FP stack to be spilled
             BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0x00, 0, ModRM_NONE, Immediate_0),
             PROPERTY0(0),