Merge pull request #3337 from fjeremic/fix-31-bit-gpr64

Correctly fill 64-bit registers on 31-bit in OOL
eclipse · Dec 17, 2018 · 2c6df63 · 2c6df63
2 parents 972f4b1 + 73add14
commit 2c6df63
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Showing 3 changed files with 40 additions and 61 deletions.
diff --git a/compiler/z/codegen/OMRCodeGenerator.cpp b/compiler/z/codegen/OMRCodeGenerator.cpp
@@ -3962,56 +3962,44 @@ OMR::Z::CodeGenerator::gprClobberEvaluate(TR::Node * node, bool force_copy, bool
    if (!self()->canClobberNodesRegister(node, 1, &data, ignoreRefCount) || force_copy)
       {
       char * CLOBBER_EVAL = "LR=Clobber_eval";
-      if ((node->getType().isInt64() || TR::Compiler->target.is64Bit() )
-         && TR::Compiler->target.is32Bit())
+      if (TR::Compiler->target.is32Bit() && !self()->use64BitRegsOn32Bit() && node->getType().isInt64())
          {
-         if (self()->use64BitRegsOn32Bit())
+         TR::RegisterPair * trgRegPair = (TR::RegisterPair *) srcRegister;
+         TR::Register * lowRegister = srcRegister->getLowOrder();
+         TR::Register * highRegister = srcRegister->getHighOrder();
+         bool allocatePair=false;
+         if (!data.canClobberLowWord())
             {
-            TR::Register * targetRegister = self()->allocate64bitRegister();
-
-            cursor = generateRRInstruction(self(), TR::InstOpCode::LGR, node, targetRegister, srcRegister);
-
-            return targetRegister;
+            lowRegister = self()->allocateRegister();
+            self()->stopUsingRegister(lowRegister); // Allocate pair will make these live again
+            allocatePair = true;
             }
-         else
+         if (!data.canClobberHighWord())
             {
-            TR::RegisterPair * trgRegPair = (TR::RegisterPair *) srcRegister;
-            TR::Register * lowRegister = srcRegister->getLowOrder();
-            TR::Register * highRegister = srcRegister->getHighOrder();
-            bool allocatePair=false;
-            if (!data.canClobberLowWord())
-               {
-               lowRegister = self()->allocateRegister();
-               self()->stopUsingRegister(lowRegister); // Allocate pair will make these live again
-               allocatePair = true;
-               }
-            if (!data.canClobberHighWord())
-               {
-               highRegister = self()->allocateRegister();
-               self()->stopUsingRegister(highRegister); // Allocate pair will make these live again
-               allocatePair = true;
-               }
+            highRegister = self()->allocateRegister();
+            self()->stopUsingRegister(highRegister); // Allocate pair will make these live again
+            allocatePair = true;
+            }
 
-            TR::RegisterPair * tempRegPair = allocatePair ? self()->allocateConsecutiveRegisterPair(lowRegister, highRegister) : trgRegPair;
-            if (!data.canClobberLowWord())
+         TR::RegisterPair * tempRegPair = allocatePair ? self()->allocateConsecutiveRegisterPair(lowRegister, highRegister) : trgRegPair;
+         if (!data.canClobberLowWord())
+            {
+            cursor = generateRRInstruction(self(), TR::InstOpCode::LR, node, tempRegPair->getLowOrder(), trgRegPair->getLowOrder());
+            if (debugObj)
                {
-               cursor = generateRRInstruction(self(), TR::InstOpCode::LR, node, tempRegPair->getLowOrder(), trgRegPair->getLowOrder());
-               if (debugObj)
-                  {
-                  debugObj->addInstructionComment(toS390RRInstruction(cursor), CLOBBER_EVAL);
-                  }
+               debugObj->addInstructionComment(toS390RRInstruction(cursor), CLOBBER_EVAL);
                }
+            }
 
-            if (!data.canClobberHighWord())
+         if (!data.canClobberHighWord())
+            {
+            cursor = generateRRInstruction(self(), TR::InstOpCode::LR, node, tempRegPair->getHighOrder(), trgRegPair->getHighOrder());
+            if (debugObj)
                {
-               cursor = generateRRInstruction(self(), TR::InstOpCode::LR, node, tempRegPair->getHighOrder(), trgRegPair->getHighOrder());
-               if (debugObj)
-                  {
-                  debugObj->addInstructionComment(toS390RRInstruction(cursor), CLOBBER_EVAL);
-                  }
+               debugObj->addInstructionComment(toS390RRInstruction(cursor), CLOBBER_EVAL);
                }
-            return tempRegPair;
             }
+         return tempRegPair;
          }
       else if (node->getOpCode().isFloat())
          {
@@ -4057,22 +4045,13 @@ OMR::Z::CodeGenerator::gprClobberEvaluate(TR::Node * node, bool force_copy, bool
       else
          {
          TR::Register * targetRegister = self()->allocateClobberableRegister(srcRegister);
-         TR::InstOpCode::Mnemonic loadRegOpCode = TR::InstOpCode::getLoadRegOpCode();
-         if (node->getType().isAddress())
-            {
-            if (TR::Compiler->target.is64Bit())
-               loadRegOpCode = TR::InstOpCode::LGR;
-            else
-               loadRegOpCode = TR::InstOpCode::LR;
-            }
-         if (self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_DisableHighWordRA) && TR::Compiler->target.is64Bit())
+         TR::InstOpCode::Mnemonic loadRegOpCode = TR::InstOpCode::getLoadRegOpCodeFromNode(self(), node);
+
+         if (srcRegister->is64BitReg())
             {
-            loadRegOpCode = TR::InstOpCode::getLoadRegOpCodeFromNode(self(), node);
-            if (srcRegister->is64BitReg())
-               {
-               loadRegOpCode = TR::InstOpCode::LGR;
-               }
+            loadRegOpCode = TR::InstOpCode::LGR;
             }
+
          cursor = generateRRInstruction(self(), loadRegOpCode, node, targetRegister, srcRegister);
 
          if (debugObj)
@@ -4083,7 +4062,7 @@ OMR::Z::CodeGenerator::gprClobberEvaluate(TR::Node * node, bool force_copy, bool
          return targetRegister;
          }
       }
-   return self()->evaluate(node);
+   return srcRegister;
    }
 
 

diff --git a/compiler/z/codegen/OMRRegisterDependency.cpp b/compiler/z/codegen/OMRRegisterDependency.cpp
@@ -959,6 +959,11 @@ TR_S390RegisterDependencyGroup::assignRegisters(TR::Instruction   *currentInstru
                      break;
                   case TR_GPR:
                      opCode = TR::InstOpCode::getLoadOpCode();
+
+                     if (virtReg->is64BitReg())
+                        {
+                        opCode = TR::InstOpCode::LG;
+                        }
                      break;
                   case TR_FPR:
                      opCode = TR::InstOpCode::LD;
@@ -970,12 +975,10 @@ TR_S390RegisterDependencyGroup::assignRegisters(TR::Instruction   *currentInstru
                      TR_ASSERT( 0, "\nRegister kind not supported in OOL spill\n");
                      break;
                   }
-
+               
                if (cg->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA) &&
                    rk != TR_FPR && rk != TR_VRF)
                   {
-                  opCode = virtReg->is64BitReg()? TR::InstOpCode::LG : TR::InstOpCode::L;
-
                   if (assignedReg->isHighWordRegister())
                      {
                      // virtReg was spilled to an HPR and now we need it spilled to stack

diff --git a/compiler/z/codegen/OMRTreeEvaluator.cpp b/compiler/z/codegen/OMRTreeEvaluator.cpp
@@ -13907,10 +13907,7 @@ OMR::Z::TreeEvaluator::lRegLoadEvaluator(TR::Node * node, TR::CodeGenerator * cg
       }
 
    // GRA needs to tell LRA about the register type
-   if (cg->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA))
-      {
-      globalReg->setIs64BitReg(true);
-      }
+   globalReg->setIs64BitReg(true);
 
    return globalReg;
    }