Migrate bad to the common codegen

eclipse · May 12, 2021 · 4a20228 · 4a20228
1 parent 8a1541b
commit 4a20228
Show file tree

Hide file tree

Showing 21 changed files with 103 additions and 108 deletions.
diff --git a/compiler/aarch64/codegen/OMRInstOpCode.enum b/compiler/aarch64/codegen/OMRInstOpCode.enum
@@ -27,8 +27,6 @@
 #include "compiler/codegen/OMRInstOpCode.enum"
 
 //		Opcode                                                          BINARY    	OPCODE    	comments
-/* UNALLOCATED */
-		bad,                                                    	/* 0x00000000	BAD       	invalid operation */
 /* Branch,exception generation and system Instruction */
 	/* Compare _ Branch (immediate) */
 		cbzw,                                                   	/* 0x34000000	CBZ       	 */

diff --git a/compiler/codegen/OMRInstOpCode.enum b/compiler/codegen/OMRInstOpCode.enum
@@ -24,4 +24,5 @@
  * definitions are permitted.
  */
 
-   assocreg,           // Register Association
+   assocreg,           // Register Association
+   bad,                // Bad Opcode
diff --git a/compiler/p/codegen/OMRInstOpCode.enum b/compiler/p/codegen/OMRInstOpCode.enum
@@ -26,7 +26,6 @@
 
 #include "compiler/codegen/OMRInstOpCode.enum"
 
-   bad,              // Illegal Opcode
    add,              // Add
    add_r,            // Add Rc=1
    addc,             // Add carrying

diff --git a/compiler/riscv/codegen/OMRInstOpCode.enum b/compiler/riscv/codegen/OMRInstOpCode.enum
@@ -26,8 +26,6 @@
 
 #include "compiler/codegen/OMRInstOpCode.enum"
 
-/* UNALLOCATED */
-		bad,
 /*
  * RISC-V instructions
  */

diff --git a/compiler/z/codegen/BinaryCommutativeAnalyser.cpp b/compiler/z/codegen/BinaryCommutativeAnalyser.cpp
@@ -350,7 +350,7 @@ TR_S390BinaryCommutativeAnalyser::genericAnalyser(TR::Node * root, TR::InstOpCod
          if (cg()->comp()->target().cpu.supportsFeature(OMR_FEATURE_S390_MISCELLANEOUS_INSTRUCTION_EXTENSION_2))
             {
             // Check for multiplications on z14
-            TR::InstOpCode::Mnemonic z14OpCode = TR::InstOpCode::BAD;
+            TR::InstOpCode::Mnemonic z14OpCode = TR::InstOpCode::bad;
 
             if(root->getOpCodeValue() == TR::lmul &&
                     firstRegister != NULL &&
@@ -367,7 +367,7 @@ TR_S390BinaryCommutativeAnalyser::genericAnalyser(TR::Node * root, TR::InstOpCod
                z14OpCode = TR::InstOpCode::MSRKC;
                }
 
-            if(z14OpCode != TR::InstOpCode::BAD)
+            if(z14OpCode != TR::InstOpCode::bad)
                {
                bool isCanClobberFirstReg = cg()->canClobberNodesRegister(firstChild);
                nodeReg = isCanClobberFirstReg ? firstRegister : cg()->allocateRegister();

diff --git a/compiler/z/codegen/BinaryEvaluator.cpp b/compiler/z/codegen/BinaryEvaluator.cpp
@@ -2350,7 +2350,7 @@ OMR::Z::TreeEvaluator::baddEvaluator(TR::Node* node, TR::CodeGenerator* cg)
    cg->evaluate(rhsChild);
 
    TR_S390BinaryCommutativeAnalyser temp(cg);
-   temp.genericAnalyser(node, TR::InstOpCode::AR, TR::InstOpCode::BAD, TR::InstOpCode::LR);
+   temp.genericAnalyser(node, TR::InstOpCode::AR, TR::InstOpCode::bad, TR::InstOpCode::LR);
 
    cg->decReferenceCount(lhsChild);
    cg->decReferenceCount(rhsChild);
@@ -2386,7 +2386,7 @@ OMR::Z::TreeEvaluator::bsubEvaluator(TR::Node* node, TR::CodeGenerator* cg)
    cg->evaluate(rhsChild);
 
    TR_S390BinaryAnalyser temp(cg);
-   temp.genericAnalyser(node, TR::InstOpCode::SR, TR::InstOpCode::BAD, TR::InstOpCode::LR);
+   temp.genericAnalyser(node, TR::InstOpCode::SR, TR::InstOpCode::bad, TR::InstOpCode::LR);
 
    return node->getRegister();
    }
@@ -2572,7 +2572,7 @@ OMR::Z::TreeEvaluator::bmulEvaluator(TR::Node* node, TR::CodeGenerator* cg)
    cg->evaluate(rhsChild);
 
    TR_S390BinaryCommutativeAnalyser temp(cg);
-   temp.genericAnalyser(node, TR::InstOpCode::MSR, TR::InstOpCode::BAD, TR::InstOpCode::LR);
+   temp.genericAnalyser(node, TR::InstOpCode::MSR, TR::InstOpCode::bad, TR::InstOpCode::LR);
 
    cg->decReferenceCount(lhsChild);
    cg->decReferenceCount(rhsChild);

diff --git a/compiler/z/codegen/InstOpCode.cpp b/compiler/z/codegen/InstOpCode.cpp
@@ -296,7 +296,7 @@ OMR::Z::InstOpCode::getEquivalentLongDisplacementMnemonic(TR::InstOpCode::Mnemon
       case TR::InstOpCode::CDS:
          return TR::InstOpCode::CDSY;
       default:
-         return TR::InstOpCode::BAD;
+         return TR::InstOpCode::bad;
       }
    }
 
@@ -564,7 +564,7 @@ OMR::Z::InstOpCode::getLoadRegOpCodeFromNode(TR::CodeGenerator *cg, TR::Node *no
 TR::InstOpCode::Mnemonic
 OMR::Z::InstOpCode::getMoveHalfWordImmOpCodeFromStoreOpCode(TR::InstOpCode::Mnemonic storeOpCode)
    {
-   TR::InstOpCode::Mnemonic mvhiOpCode = TR::InstOpCode::BAD;
+   TR::InstOpCode::Mnemonic mvhiOpCode = TR::InstOpCode::bad;
    if (storeOpCode == TR::InstOpCode::ST)
       mvhiOpCode = TR::InstOpCode::MVHI;
    else if (storeOpCode == TR::InstOpCode::STG)

diff --git a/compiler/z/codegen/OMRInstOpCode.enum b/compiler/z/codegen/OMRInstOpCode.enum
@@ -28,7 +28,6 @@
 
    /* Pseudo Instructions */
 
-   BAD,                 // Bad Opcode
    BREAK,               // Breakpoint (debugger)
    DC,                  // DC
    DC2,                 // DC2

diff --git a/compiler/z/codegen/OMRInstOpCode.hpp b/compiler/z/codegen/OMRInstOpCode.hpp
@@ -397,7 +397,7 @@ class InstOpCode: public OMR::InstOpCode
    {
    protected:
 
-   InstOpCode():  OMR::InstOpCode(BAD)  {}
+   InstOpCode():  OMR::InstOpCode(bad)  {}
    InstOpCode(Mnemonic m): OMR::InstOpCode(m)  {}
 
    public:

diff --git a/compiler/z/codegen/OMRInstOpCodeProperties.hpp b/compiler/z/codegen/OMRInstOpCodeProperties.hpp
@@ -37,8 +37,8 @@
    },
 
    {
-   /* .mnemonic    = */ OMR::InstOpCode::BAD,
-   /* .name        = */ "BAD",
+   /* .mnemonic    = */ OMR::InstOpCode::bad,
+   /* .name        = */ "bad",
    /* .description = */ "Bad Opcode",
    /* .opcode[0]   = */ 0x00,
    /* .opcode[1]   = */ 0x00,

diff --git a/compiler/z/codegen/OMRMachine.cpp b/compiler/z/codegen/OMRMachine.cpp
@@ -265,9 +265,9 @@ OMR::Z::Machine::registerExchange(TR::CodeGenerator* cg,
       {
       TR_ASSERT_FATAL(targetReg->getAssignedRegister()->is64BitReg() == sourceReg->getAssignedRegister()->is64BitReg(), "Attempting register exchange with one 64-bit register (%s) and one 32-bit register (%s)", getRegisterName(sourceReg, cg), getRegisterName(targetReg, cg));
 
-      TR::InstOpCode::Mnemonic opLoadReg = TR::InstOpCode::BAD;
-      TR::InstOpCode::Mnemonic opLoad = TR::InstOpCode::BAD;
-      TR::InstOpCode::Mnemonic opStore = TR::InstOpCode::BAD;
+      TR::InstOpCode::Mnemonic opLoadReg = TR::InstOpCode::bad;
+      TR::InstOpCode::Mnemonic opLoad = TR::InstOpCode::bad;
+      TR::InstOpCode::Mnemonic opStore = TR::InstOpCode::bad;
 
       if (targetReg->getAssignedRegister()->is64BitReg())
          {

diff --git a/compiler/z/codegen/OMRMemoryReference.cpp b/compiler/z/codegen/OMRMemoryReference.cpp
@@ -1974,7 +1974,7 @@ TR::Register *OMR::Z::MemoryReference::swapBaseRegister(TR::Register *br, TR::Co
 TR::Instruction *
 OMR::Z::MemoryReference::handleLargeOffset(TR::Node * node, TR::MemoryReference *interimMemoryReference, TR::Register *tempTargetRegister, TR::CodeGenerator * cg, TR::Instruction * preced)
    {
-   TR::InstOpCode::Mnemonic op = TR::InstOpCode::BAD;
+   TR::InstOpCode::Mnemonic op = TR::InstOpCode::bad;
 
    if (_offset > MINLONGDISP && _offset < MAXLONGDISP)
       {
@@ -2951,7 +2951,7 @@ OMR::Z::MemoryReference::generateBinaryEncoding(uint8_t * cursor, TR::CodeGenera
       auto longDisplacementMnemonic = TR::InstOpCode::getEquivalentLongDisplacementMnemonic(instr->getOpCodeValue());
 
       if ((displacement < MAXLONGDISP && displacement > MINLONGDISP)
-         && (longDisplacementMnemonic != TR::InstOpCode::BAD
+         && (longDisplacementMnemonic != TR::InstOpCode::bad
             || instructionFormat == TR::Instruction::IsRXY
             || instructionFormat == TR::Instruction::IsRXYb
             || instructionFormat == TR::Instruction::IsRSY
@@ -2970,7 +2970,7 @@ OMR::Z::MemoryReference::generateBinaryEncoding(uint8_t * cursor, TR::CodeGenera
          // formats and S390*Instruction formats
          instructionFormat = TR::Instruction::IsRXY;
 
-         if (longDisplacementMnemonic != TR::InstOpCode::BAD)
+         if (longDisplacementMnemonic != TR::InstOpCode::bad)
             {
             TR::DebugCounter::incStaticDebugCounter(comp, TR::DebugCounter::debugCounterName(comp, "z/memref/long-displacement-upgrade/(%s)", comp->signature()));
             }

diff --git a/compiler/z/codegen/OMRPeephole.cpp b/compiler/z/codegen/OMRPeephole.cpp
@@ -762,7 +762,7 @@ OMR::Z::Peephole::tryToReduce64BitShiftTo32BitShift()
 
    if (performTransformation(self()->comp(), "O^O S390 PEEPHOLE: Reverting int shift at %p from SLLG/SLAG/S[LR][LA]K to SLL/SLA/SRL/SRA.\n", shiftInst))
       {
-      TR::InstOpCode::Mnemonic newOpCode = TR::InstOpCode::BAD;
+      TR::InstOpCode::Mnemonic newOpCode = TR::InstOpCode::bad;
       switch (oldOpCode)
          {
          case TR::InstOpCode::SLLG: