RISC-V: convert some TR_ASSERT()s to TR_ASSERT_FATAL()s

eclipse · Jun 16, 2021 · 50dcd28 · 50dcd28
1 parent 8a7f2c0
commit 50dcd28
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Showing 3 changed files with 15 additions and 15 deletions.
diff --git a/compiler/riscv/codegen/OMRMachine.cpp b/compiler/riscv/codegen/OMRMachine.cpp
@@ -465,8 +465,8 @@ static void registerCopy(TR::Instruction *precedingInstruction,
                          TR::RealRegister *sourceReg,
                          TR::CodeGenerator *cg)
    {
-   TR_ASSERT(sourceReg->getKind() == rk, "Source register kind mismatch.");
-   TR_ASSERT(sourceReg->getKind() == targetReg->getKind(), "Source and target register kind mismatch.");
+   TR_ASSERT_FATAL(sourceReg->getKind() == rk, "Source register kind mismatch.");
+   TR_ASSERT_FATAL(sourceReg->getKind() == targetReg->getKind(), "Source and target register kind mismatch.");
 
    TR::Node *node = precedingInstruction->getNode();
    switch (rk)
@@ -475,11 +475,11 @@ static void registerCopy(TR::Instruction *precedingInstruction,
          generateITYPE(TR::InstOpCode::_addi, node, targetReg, sourceReg, 0, cg, precedingInstruction);
          break;
       case TR_FPR:
-         TR_ASSERT(sourceReg->isSinglePrecision() == targetReg->isSinglePrecision(), "Source and target register size mismatch");
+         TR_ASSERT_FATAL(sourceReg->isSinglePrecision() == targetReg->isSinglePrecision(), "Source and target register size mismatch");
          generateRTYPE(sourceReg->isSinglePrecision() ? TR::InstOpCode::_fsgnj_s : TR::InstOpCode::_fsgnj_d, node, targetReg, sourceReg, sourceReg, cg, precedingInstruction);
          break;
       default:
-         TR_ASSERT(false, "Unsupported RegisterKind.");
+         TR_ASSERT_FATAL(false, "Unsupported RegisterKind.");
          break;
       }
    }

diff --git a/compiler/riscv/codegen/RVInstruction.cpp b/compiler/riscv/codegen/RVInstruction.cpp
@@ -484,7 +484,7 @@ uint8_t *TR::JtypeInstruction::generateBinaryEncoding() {
 
    if (getSymbolReference() != nullptr)
       {
-      TR_ASSERT(getLabelSymbol() == nullptr, "Both symbol reference and symbol set in J-type instruction");
+      TR_ASSERT_FATAL(getLabelSymbol() == nullptr, "Both symbol reference and symbol set in J-type instruction");
       TR::ResolvedMethodSymbol *sym = getSymbolReference()->getSymbol()->getResolvedMethodSymbol();
       TR_ResolvedMethod *resolvedMethod = sym == NULL ? NULL : sym->getResolvedMethod();
 
@@ -511,7 +511,7 @@ uint8_t *TR::JtypeInstruction::generateBinaryEncoding() {
          }
       }
 
-   TR_ASSERT(VALID_UJTYPE_IMM(offset), "Jump offset out of range");
+   TR_ASSERT_FATAL(VALID_UJTYPE_IMM(offset), "Jump offset out of range");
    *iPtr = TR_RISCV_UJTYPE (getOpCode().getMnemonic(), getTargetRegister(), offset);
 
    cursor += RISCV_INSTRUCTION_LENGTH;

diff --git a/compiler/riscv/codegen/RVSystemLinkage.cpp b/compiler/riscv/codegen/RVSystemLinkage.cpp
@@ -205,7 +205,7 @@ static void mapSingleParameter(TR::ParameterSymbol *parameter, uint32_t &stackIn
       }
    else
       { // in caller's frame -- always 8-byte aligned
-      TR_ASSERT((stackIndex & 7) == 0, "Unaligned stack index.");
+      TR_ASSERT_FATAL((stackIndex & 7) == 0, "Unaligned stack index.");
       parameter->setParameterOffset(stackIndex);
       stackIndex += 8;
       }
@@ -305,10 +305,10 @@ TR::RVSystemLinkage::mapStack(TR::ResolvedMethodSymbol *method)
                }
             break;
          case TR::Aggregate:
-            TR_ASSERT(false, "Function parameters of aggregate types are not currently supported on RISC-V.");
+            TR_ASSERT_FATAL(false, "Function parameters of aggregate types are not currently supported on RISC-V.");
             break;
          default:
-            TR_ASSERT(false, "Unknown parameter type.");
+            TR_ASSERT_FATAL(false, "Unknown parameter type.");
          }
       }
 
@@ -355,10 +355,10 @@ TR::RVSystemLinkage::mapStack(TR::ResolvedMethodSymbol *method)
                }
             break;
          case TR::Aggregate:
-            TR_ASSERT(false, "Function parameters of aggregate types are not currently supported on RISC-V.");
+            TR_ASSERT_FATAL(false, "Function parameters of aggregate types are not currently supported on RISC-V.");
             break;
          default:
-            TR_ASSERT(false, "Unknown parameter type.");
+            TR_ASSERT_FATAL(false, "Unknown parameter type.");
          }
       }
    }
@@ -460,10 +460,10 @@ TR::RVSystemLinkage::createPrologue(TR::Instruction *cursor, List<TR::ParameterS
                }
             break;
          case TR::Aggregate:
-            TR_ASSERT(false, "Function parameters of aggregate types are not currently supported on AArch64.");
+            TR_ASSERT_FATAL(false, "Function parameters of aggregate types are not currently supported on RISC-V.");
             break;
          default:
-            TR_ASSERT(false, "Unknown parameter type.");
+            TR_ASSERT_FATAL(false, "Unknown parameter type.");
          }
       }
 
@@ -572,7 +572,7 @@ int32_t TR::RVSystemLinkage::buildArgs(TR::Node *callNode,
             break;
 
          default:
-            TR_ASSERT(false, "Argument type %s is not supported\n", childType.toString());
+            TR_ASSERT_FATAL(false, "Argument type %s is not supported\n", childType.toString());
          }
       }
 
@@ -891,7 +891,7 @@ TR::Register *TR::RVSystemLinkage::buildDispatch(TR::Node *callNode)
          break;
       default:
          retReg = NULL;
-         TR_ASSERT(false, "Unsupported direct call Opcode.");
+         TR_ASSERT_FATAL(false, "Unsupported direct call Opcode.");
       }
 
    callNode->setRegister(retReg);