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Unify doRegisterAssignment on all platforms except x86
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Now that we have gotten `doRegisterAssignment` to look exactly the same
on several platforms we can deprecte the platform specific versions.
Unfortunately on x86 we seem to be doing something completely different
from all the other platforms, so in general tackling register allocation
on x86 will need to be done separately.
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@fjeremic
fjeremic committed Apr 30, 2021
1 parent decbc18 commit 6ed62c2
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Showing 12 changed files with 85 additions and 349 deletions.
68 changes: 1 addition & 67 deletions compiler/aarch64/codegen/OMRCodeGenerator.cpp
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Expand Up @@ -48,8 +48,7 @@
OMR::ARM64::CodeGenerator::CodeGenerator(TR::Compilation *comp) :
OMR::CodeGenerator(comp),
_dataSnippetList(getTypedAllocator<TR::ARM64ConstantDataSnippet*>(comp->allocator())),
_outOfLineCodeSectionList(getTypedAllocator<TR_ARM64OutOfLineCodeSection*>(comp->allocator())),
_firstTimeLiveOOLRegisterList(NULL)
_outOfLineCodeSectionList(getTypedAllocator<TR_ARM64OutOfLineCodeSection*>(comp->allocator()))
{
}

Expand Down Expand Up @@ -193,71 +192,6 @@ OMR::ARM64::CodeGenerator::endInstructionSelection()
}
}

void
OMR::ARM64::CodeGenerator::doRegisterAssignment(TR_RegisterKinds kindsToAssign)
{
// Registers are assigned in backward direction

TR::Compilation *comp = self()->comp();

TR::Instruction *instructionCursor = self()->getAppendInstruction();

if (!self()->isOutOfLineColdPath())
{
// Allocates these lists when the register assignment starts.
// As doRegisterAssignment is called mutiple times for the cold path of OutOfLineCodeSections,
// we do allocation only when we are not in the cold path.
TR::list<TR::Register*> *firstTimeLiveOOLRegisterList = new (self()->trHeapMemory()) TR::list<TR::Register*>(getTypedAllocator<TR::Register*>(self()->comp()->allocator()));
self()->setFirstTimeLiveOOLRegisterList(firstTimeLiveOOLRegisterList);

TR::list<TR::Register*> *spilledRegisterList = new (self()->trHeapMemory()) TR::list<TR::Register*>(getTypedAllocator<TR::Register*>(comp->allocator()));
self()->setSpilledRegisterList(spilledRegisterList);
}

if (self()->getDebug())
self()->getDebug()->startTracingRegisterAssignment();

while (instructionCursor)
{
TR::Instruction *prevInstruction = instructionCursor->getPrev();

self()->tracePreRAInstruction(instructionCursor);

instructionCursor->assignRegisters(TR_GPR);

// Maintain Internal Control Flow Depth
// Track internal control flow on labels
if (instructionCursor->isLabel())
{
TR::ARM64LabelInstruction *li = (TR::ARM64LabelInstruction *)instructionCursor;

if (li->getLabelSymbol() != NULL)
{
if (li->getLabelSymbol()->isStartInternalControlFlow())
{
self()->decInternalControlFlowNestingDepth();
}
if (li->getLabelSymbol()->isEndInternalControlFlow())
{
self()->incInternalControlFlowNestingDepth();
}
}
}

self()->freeUnlatchedRegisters();
self()->buildGCMapsForInstructionAndSnippet(instructionCursor);

self()->tracePostRAInstruction(instructionCursor);

instructionCursor = prevInstruction;
}

if (self()->getDebug())
{
self()->getDebug()->stopTracingRegisterAssignment();
}
}

void
OMR::ARM64::CodeGenerator::generateBinaryEncodingPrePrologue(TR_ARM64BinaryEncodingData &data)
{
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20 changes: 0 additions & 20 deletions compiler/aarch64/codegen/OMRCodeGenerator.hpp
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Expand Up @@ -171,12 +171,6 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator
*/
void endInstructionSelection();

/**
* @brief AArch64 local register assignment pass
* @param[in] kindsToAssign : mask of register kinds to assign in this pass
*/
void doRegisterAssignment(TR_RegisterKinds kindsToAssign);

/**
* @brief AArch64 binary encoding pass
*/
Expand Down Expand Up @@ -323,20 +317,6 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator
*/
void setIsOutOfLineHotPath(bool v) { _flags.set(IsOutOfLineHotPath, v);}

/**
* @brief Returns the list of registers which is assigned first time in OOL cold path
*
* @return the list of registers which is assigned first time in OOL cold path
*/
TR::list<TR::Register*> *getFirstTimeLiveOOLRegisterList() {return _firstTimeLiveOOLRegisterList;}
/**
* @brief Sets the list of registers which is assigned first time in OOL cold path
*
* @param r : the list of registers which is assigned first time in OOL cold path
* @return the list of registers
*/
TR::list<TR::Register*> *setFirstTimeLiveOOLRegisterList(TR::list<TR::Register*> *r) {return _firstTimeLiveOOLRegisterList = r;}

/**
* @brief Picks register
* @param[in] regCan : register candidate
Expand Down
58 changes: 0 additions & 58 deletions compiler/arm/codegen/OMRCodeGenerator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -348,64 +348,6 @@ void OMR::ARM::CodeGenerator::endInstructionSelection()
}
}

void OMR::ARM::CodeGenerator::doRegisterAssignment(TR_RegisterKinds kindsToAssign)
{
TR::Compilation *comp = self()->comp();

if (comp->getOption(TR_TraceCG))
diagnostic("\nPerforming Register Assignment:\n");

TR::Instruction *instructionCursor = self()->getAppendInstruction();

TR::list<TR::Register*> *spilledRegisterList = new (self()->trHeapMemory()) TR::list<TR::Register*>(getTypedAllocator<TR::Register*>(comp->allocator()));
self()->setSpilledRegisterList(spilledRegisterList);

while (instructionCursor)
{
// TODO Use cross-platform register assignment tracing facility
if (comp->getOption(TR_TraceCG))
{
diagnostic("\nassigning registers for [" POINTER_PRINTF_FORMAT "]:", instructionCursor);
self()->getDebug()->print(comp->getOutFile(), instructionCursor);
}

TR::Instruction *prevInstruction = instructionCursor->getPrev();
TR::Instruction *nextInstruction = instructionCursor->getNext();
instructionCursor->assignRegisters(TR_GPR);
// Maintain Internal Control Flow Depth
// Track internal control flow on labels
if (instructionCursor->isLabel())
{
TR::ARMLabelInstruction *li = (TR::ARMLabelInstruction *)instructionCursor;

if (li->getLabelSymbol() != NULL)
{
if (li->getLabelSymbol()->isStartInternalControlFlow())
{
self()->decInternalControlFlowNestingDepth();
}
if (li->getLabelSymbol()->isEndInternalControlFlow())
{
self()->incInternalControlFlowNestingDepth();
}
}
}
self()->freeUnlatchedRegisters();
self()->buildGCMapsForInstructionAndSnippet(instructionCursor);

if (comp->getOption(TR_TraceCG))
{
diagnostic("\npost-assignment instruction(s):");
TR::Instruction *instr = prevInstruction ? prevInstruction->getNext() : instructionCursor;
for (; instr != nextInstruction; instr = instr->getNext())
self()->getDebug()->print(comp->getOutFile(), instr);
diagnostic("\n");
}

instructionCursor = prevInstruction;
}
}

void OMR::ARM::CodeGenerator::doBinaryEncoding()
{
TR::Compilation *comp = self()->comp();
Expand Down
1 change: 0 additions & 1 deletion compiler/arm/codegen/OMRCodeGenerator.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -124,7 +124,6 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator

void beginInstructionSelection();
void endInstructionSelection();
void doRegisterAssignment(TR_RegisterKinds kindsToAssign);
void doBinaryEncoding();

void emitDataSnippets();
Expand Down
64 changes: 64 additions & 0 deletions compiler/codegen/OMRCodeGenerator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -218,7 +218,9 @@ OMR::CodeGenerator::CodeGenerator(TR::Compilation *comp) :
_spill8FreeList(getTypedAllocator<TR_BackingStore*>(comp->allocator())),
_spill16FreeList(getTypedAllocator<TR_BackingStore*>(comp->allocator())),
_internalPointerSpillFreeList(getTypedAllocator<TR_BackingStore*>(comp->allocator())),
_firstTimeLiveOOLRegisterList(NULL),
_spilledRegisterList(NULL),
_afterRA(false),
_referencedRegistersList(NULL),
_variableSizeSymRefPendingFreeList(getTypedAllocator<TR::SymbolReference*>(comp->allocator())),
_variableSizeSymRefFreeList(getTypedAllocator<TR::SymbolReference*>(comp->allocator())),
Expand Down Expand Up @@ -836,6 +838,68 @@ OMR::CodeGenerator::doInstructionSelection()
}
}

void
OMR::CodeGenerator::doRegisterAssignment(TR_RegisterKinds kindsToAssign)
{
TR::Instruction *prevInstr = NULL;
TR::Instruction *currInstr = self()->getAppendInstruction();

auto *firstTimeLiveOOLRegisterList = new (self()->trHeapMemory()) TR::list<TR::Register*>(getTypedAllocator<TR::Register*>(self()->comp()->allocator()));
self()->setFirstTimeLiveOOLRegisterList(firstTimeLiveOOLRegisterList);

auto *spilledRegisterList = new (self()->trHeapMemory()) TR::list<TR::Register*>(getTypedAllocator<TR::CFGEdge*>(self()->comp()->allocator()));
self()->setSpilledRegisterList(spilledRegisterList);

if (self()->getDebug())
{
self()->getDebug()->startTracingRegisterAssignment();
}

while (currInstr)
{
prevInstr = currInstr->getPrev();

self()->tracePreRAInstruction(currInstr);

if (currInstr->getNode()->getOpCodeValue() == TR::BBEnd)
{
self()->comp()->setCurrentBlock(currInstr->getNode()->getBlock());
}

// Main register assignment procedure
currInstr->assignRegisters(TR_GPR);

if (currInstr->isLabel())
{
if (currInstr->getLabelSymbol() != NULL)
{
if (currInstr->getLabelSymbol()->isStartInternalControlFlow())
{
self()->decInternalControlFlowNestingDepth();
}
if (currInstr->getLabelSymbol()->isEndInternalControlFlow())
{
self()->incInternalControlFlowNestingDepth();
}
}
}

self()->freeUnlatchedRegisters();
self()->buildGCMapsForInstructionAndSnippet(currInstr);

self()->tracePostRAInstruction(currInstr);

currInstr = prevInstr;
}

_afterRA = true;

if (self()->getDebug())
{
self()->getDebug()->stopTracingRegisterAssignment();
}
}

bool
OMR::CodeGenerator::use64BitRegsOn32Bit()
{
Expand Down
19 changes: 19 additions & 0 deletions compiler/codegen/OMRCodeGenerator.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1085,6 +1085,21 @@ class OMR_EXTENSIBLE CodeGenerator
TR::list<TR_BackingStore*>& getCollectedSpillList() {return _collectedSpillList;}
TR::list<TR_BackingStore*>& getAllSpillList() {return _allSpillList;}

/**
* @brief Returns the list of registers which is assigned first time in OOL cold path
*
* @return the list of registers which is assigned first time in OOL cold path
*/
TR::list<TR::Register*> *getFirstTimeLiveOOLRegisterList() {return _firstTimeLiveOOLRegisterList;}

/**
* @brief Sets the list of registers which is assigned first time in OOL cold path
*
* @param r : the list of registers which is assigned first time in OOL cold path
* @return the list of registers
*/
TR::list<TR::Register*> *setFirstTimeLiveOOLRegisterList(TR::list<TR::Register*> *r) {return _firstTimeLiveOOLRegisterList = r;}

TR::list<TR::Register*> *getSpilledRegisterList() {return _spilledRegisterList;}
TR::list<TR::Register*> *setSpilledRegisterList(TR::list<TR::Register*> *r) {return _spilledRegisterList = r;}

Expand Down Expand Up @@ -1953,6 +1968,7 @@ class OMR_EXTENSIBLE CodeGenerator

int32_t _accumulatorNodeUsage;

TR::list<TR::Register*> *_firstTimeLiveOOLRegisterList;
TR::list<TR::Register*> *_spilledRegisterList;
TR::list<OMR::RegisterUsage*> *_referencedRegistersList;
int32_t _currentPathDepth;
Expand Down Expand Up @@ -2003,6 +2019,9 @@ class OMR_EXTENSIBLE CodeGenerator

protected:

/// Determines whether register allocation has been completed
bool _afterRA;

bool _disableInternalPointers;

TR::RegisterIterator *_gpRegisterIterator;
Expand Down
56 changes: 0 additions & 56 deletions compiler/p/codegen/OMRCodeGenerator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -540,62 +540,6 @@ OMR::Power::CodeGenerator::mulDecompositionCostIsJustified(
}
}

void OMR::Power::CodeGenerator::doRegisterAssignment(TR_RegisterKinds kindsToAssign)
{
TR::Instruction *prevInstruction;

// gprs, fprs, and ccrs are all assigned in backward direction

TR::Instruction *instructionCursor = self()->getAppendInstruction();

TR::Block *currBlock = NULL;
TR::Instruction * currBBEndInstr = instructionCursor;

TR::list<TR::Register*> *spilledRegisterList = new (self()->trHeapMemory()) TR::list<TR::Register*>(getTypedAllocator<TR::Register*>(self()->comp()->allocator()));
self()->setSpilledRegisterList(spilledRegisterList);

if (self()->getDebug())
self()->getDebug()->startTracingRegisterAssignment();

while (instructionCursor)
{
prevInstruction = instructionCursor->getPrev();

self()->tracePreRAInstruction(instructionCursor);

instructionCursor->assignRegisters(TR_GPR);

// Maintain Internal Control Flow Depth
// Track internal control flow on labels
if (instructionCursor->isLabel())
{
TR::PPCLabelInstruction *li = (TR::PPCLabelInstruction *)instructionCursor;

if (li->getLabelSymbol() != NULL)
{
if (li->getLabelSymbol()->isStartInternalControlFlow())
{
self()->decInternalControlFlowNestingDepth();
}
if (li->getLabelSymbol()->isEndInternalControlFlow())
{
self()->incInternalControlFlowNestingDepth();
}
}
}

self()->freeUnlatchedRegisters();
self()->buildGCMapsForInstructionAndSnippet(instructionCursor);

self()->tracePostRAInstruction(instructionCursor);

instructionCursor = prevInstruction;
}

if (self()->getDebug())
self()->getDebug()->stopTracingRegisterAssignment();
}

TR::Instruction *OMR::Power::CodeGenerator::generateNop(TR::Node *n, TR::Instruction *preced, TR_NOPKind nopKind)
{
TR::InstOpCode::Mnemonic nop;
Expand Down
1 change: 0 additions & 1 deletion compiler/p/codegen/OMRCodeGenerator.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -196,7 +196,6 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator

void beginInstructionSelection();
void endInstructionSelection();
void doRegisterAssignment(TR_RegisterKinds kindsToAssign);
void doBinaryEncoding();
void processRelocations();
void expandInstructions();
Expand Down
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