Replace instantiations of TR_ARMOpCode with TR::InstOpCode

Now that we have multiple inheritence properly working, we can replace all uses of `TR_ARMOpCode` with `TR::InstOpCode`.
eclipse · Jun 8, 2021 · 70953c3 · 70953c3
1 parent 86cef15
commit 70953c3
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Showing 10 changed files with 18 additions and 35 deletions.
diff --git a/compiler/arm/codegen/ARMBinaryEncoding.cpp b/compiler/arm/codegen/ARMBinaryEncoding.cpp
@@ -624,7 +624,7 @@ uint8_t *TR::ARMVirtualGuardNOPInstruction::generateBinaryEncoding()
        // 2) We might want to re-enable the code path and unpatch, in which case we would have to know what the old instruction was
          cg()->comp()->compileRelocatableCode())
       {
-      TR_ARMOpCode opCode(ARMOp_nop);
+      TR::InstOpCode opCode(ARMOp_nop);
       opCode.copyBinaryToBuffer(cursor);
       length = ARM_INSTRUCTION_LENGTH;
       }

diff --git a/compiler/arm/codegen/ARMDebug.cpp b/compiler/arm/codegen/ARMDebug.cpp
@@ -134,7 +134,7 @@ static const char * opCodeToVFPMap[] =
 #endif
 
 static const char *
-getExtraVFPInstrSpecifiers(TR_ARMOpCode *opCode)
+getExtraVFPInstrSpecifiers(TR::InstOpCode *opCode)
    {
 #define FIRST_VFP_INSTR		ARMOp_fabsd
 
@@ -1795,7 +1795,7 @@ static const char * opCodeToNameMap[] =
    };
 
 const char *
-TR_Debug::getOpCodeName(TR_ARMOpCode * opCode)
+TR_Debug::getOpCodeName(TR::InstOpCode * opCode)
    {
    return opCodeToNameMap[opCode->getOpCodeValue()];
    }

diff --git a/compiler/arm/codegen/ARMGenerateInstructions.cpp b/compiler/arm/codegen/ARMGenerateInstructions.cpp
@@ -138,7 +138,7 @@ TR::Instruction *generateMemSrc1Instruction(TR::CodeGenerator      *cg,
                                            TR::Instruction        *prev)
    {
 #if (defined(__VFP_FP__) && !defined(__SOFTFP__))
-   TR_ARMOpCode    opCode(op);
+   TR::InstOpCode    opCode(op);
    if (opCode.isVFPOp())
       {
       mf->fixupVFPOffset(node, cg);
@@ -159,7 +159,7 @@ TR::Instruction *generateTrg1MemInstruction(TR::CodeGenerator      *cg,
                                            TR::Instruction        *prev)
    {
 #if (defined(__VFP_FP__) && !defined(__SOFTFP__))
-   TR_ARMOpCode    opCode(op);
+   TR::InstOpCode    opCode(op);
    if (opCode.isVFPOp())
       {
       mf->fixupVFPOffset(node, cg);
@@ -209,7 +209,7 @@ TR::Instruction *generateSrc1ImmInstruction(TR::CodeGenerator *cg,
                                            uint32_t          rotate,
                                            TR::Instruction   *prev)
    {
-   TR_ARMOpCode    opCode(op);
+   TR::InstOpCode    opCode(op);
    TR_ARMOperand2 *operand = new (cg->trHeapMemory()) TR_ARMOperand2(base, rotate);
    if (opCode.isVFPOp())
       {
@@ -234,7 +234,7 @@ TR::Instruction *generateSrc2Instruction(TR::CodeGenerator *cg,
                                         TR::Register      *s2reg,
                                         TR::Instruction   *prev)
    {
-   TR_ARMOpCode    opCode(op);
+   TR::InstOpCode    opCode(op);
    TR_ARMOperand2 *operand = new (cg->trHeapMemory()) TR_ARMOperand2(ARMOp2Reg, s2reg);
    if (opCode.isVFPOp())
       {

diff --git a/compiler/arm/codegen/ARMInstruction.hpp b/compiler/arm/codegen/ARMInstruction.hpp
@@ -1350,9 +1350,9 @@ class ARMControlFlowInstruction : public TR::Instruction
    int32_t _numSources;
    int32_t _numTargets;
    TR::LabelSymbol *_label;
-   TR_ARMOpCode _opCode2;
-   TR_ARMOpCode _opCode3;
-   TR_ARMOpCode _cmpOp;
+   TR::InstOpCode _opCode2;
+   TR::InstOpCode _opCode3;
+   TR::InstOpCode _cmpOp;
 
    public:
 
@@ -1401,15 +1401,15 @@ class ARMControlFlowInstruction : public TR::Instruction
    TR::LabelSymbol *getLabelSymbol()                     {return _label;}
    TR::LabelSymbol *setLabelSymbol(TR::LabelSymbol *sym)  {return (_label = sym);}
 
-   TR_ARMOpCode& getOpCode2()                      {return _opCode2;}
+   TR::InstOpCode& getOpCode2()                      {return _opCode2;}
    TR_ARMOpCodes getOpCode2Value()                 {return _opCode2.getOpCodeValue();}
    TR_ARMOpCodes setOpCode2Value(TR_ARMOpCodes op) {return (_opCode2.setOpCodeValue(op));}
 
-   TR_ARMOpCode& getOpCode3()                      {return _opCode3;}
+   TR::InstOpCode& getOpCode3()                      {return _opCode3;}
    TR_ARMOpCodes getOpCode3Value()                 {return _opCode3.getOpCodeValue();}
    TR_ARMOpCodes setOpCode3Value(TR_ARMOpCodes op) {return (_opCode3.setOpCodeValue(op));}
 
-   TR_ARMOpCode& getCmpOp()                      {return _cmpOp;}
+   TR::InstOpCode& getCmpOp()                      {return _cmpOp;}
    TR_ARMOpCodes getCmpOpValue()                 {return _cmpOp.getOpCodeValue();}
    TR_ARMOpCodes setCmpOpValue(TR_ARMOpCodes op) {return (_cmpOp.setOpCodeValue(op));}
 

diff --git a/compiler/arm/codegen/OMRCodeGenerator.hpp b/compiler/arm/codegen/OMRCodeGenerator.hpp
@@ -88,7 +88,6 @@ namespace TR { class Machine; }
 namespace TR { class CodeGenerator; }
 namespace TR { struct ARMLinkageProperties; }
 namespace TR { class ARMImmInstruction; }
-class TR_ARMOpCode;
 namespace TR { class ARMConstantDataSnippet; }
 class TR_ARMLoadLabelItem;
 class TR_BitVector;

diff --git a/compiler/arm/codegen/OMRInstruction.hpp b/compiler/arm/codegen/OMRInstruction.hpp
@@ -86,7 +86,7 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
 
    virtual Kind getKind() { return IsNotExtended; }
 
-   TR_ARMOpCode& getOpCode()                       {return _opcode;}
+   TR::InstOpCode& getOpCode()                       {return _opcode;}
    TR_ARMOpCodes getOpCodeValue()                  {return _opcode.getOpCodeValue();}
    TR_ARMOpCodes getRecordFormOpCode()             {return _opcode.getRecordFormOpCodeValue();}
    TR_ARMOpCodes setOpCodeValue(TR_ARMOpCodes op)  {return _opcode.setOpCodeValue(op);}
@@ -210,7 +210,7 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
 
 
    private:
-      TR_ARMOpCode   _opcode;
+      TR::InstOpCode   _opcode;
       TR_ARMConditionCode                  _conditionCode;
       TR::RegisterDependencyConditions *_conditions;
       bool        _asyncBranch;

diff --git a/compiler/arm/codegen/StackCheckFailureSnippet.cpp b/compiler/arm/codegen/StackCheckFailureSnippet.cpp
@@ -35,7 +35,7 @@
 uint8_t *storeArgumentItem(TR_ARMOpCodes op, uint8_t *buffer, TR::RealRegister *reg, int32_t offset, TR::CodeGenerator *cg)
    {
    TR::RealRegister *stackPtr = cg->machine()->getRealRegister(cg->getLinkage()->getProperties().getStackPointerRegister());
-   TR_ARMOpCode       opCode(op);
+   TR::InstOpCode       opCode(op);
    opCode.copyBinaryToBuffer(buffer);
    reg->setRegisterFieldRD(toARMCursor(buffer));
    stackPtr->setRegisterFieldRN(toARMCursor(buffer));
@@ -50,7 +50,7 @@ uint8_t *loadArgumentItem(TR_ARMOpCodes op, uint8_t *buffer, TR::RealRegister *r
    {
    TR_ASSERT(0, "fix loadArgumentItem");
    TR::RealRegister *stackPtr = cg->machine()->getRealRegister(cg->getLinkage()->getProperties().getStackPointerRegister());
-   TR_ARMOpCode       opCode(op);
+   TR::InstOpCode       opCode(op);
    opCode.copyBinaryToBuffer(buffer);
    reg->setRegisterFieldRT(toARMCursor(buffer));
    stackPtr->setRegisterFieldRD(toARMCursor(buffer));

diff --git a/compiler/codegen/OMRInstOpCode.cpp b/compiler/codegen/OMRInstOpCode.cpp
@@ -21,14 +21,6 @@
 
 #include "compiler/codegen/InstOpCode.hpp"
 
-uint8_t *
-OMR::InstOpCode::copyBinaryToBuffer(
-      Mnemonic m,
-      uint8_t *cursor)
-   {
-   return cursor;
-   }
-
 const char *
 OMR::InstOpCode::getOpCodeName(Mnemonic m)
    {

diff --git a/compiler/codegen/OMRInstOpCode.hpp b/compiler/codegen/OMRInstOpCode.hpp
@@ -61,13 +61,6 @@ class InstOpCode
 
    static int32_t getNumOpCodes() { return NumOpCodes; }
 
-   /*
-    * Copies the encoded binary representation of a given mnemonic to the
-    * provided buffer.  This will copy at most length() bytes.
-    *
-    * Returns the cursor position after the bytes have been copied.
-    */
-   static uint8_t *copyBinaryToBuffer(Mnemonic m, uint8_t *cursor);
    static const char *getOpCodeName(Mnemonic m);
    static const char *getMnemonicName(Mnemonic m);
 

diff --git a/compiler/ras/Debug.hpp b/compiler/ras/Debug.hpp
@@ -217,7 +217,6 @@ namespace TR { class PPCCallSnippet; }
 #endif
 
 
-class TR_ARMOpCode;
 namespace TR { class ARMLabelInstruction; }
 namespace TR { class ARMConditionalBranchInstruction; }
 namespace TR { class ARMVirtualGuardNOPInstruction; }
@@ -627,7 +626,7 @@ class TR_Debug
 #if defined(TR_TARGET_ARM)
    virtual void printARMDelayedOffsetInstructions(TR::FILE *pOutFile, TR::ARMMemInstruction *instr);
    virtual void printARMHelperBranch(TR::SymbolReference *symRef, uint8_t *cursor, TR::FILE *outFile, const char * opcodeName = "bl");
-   virtual const char * getOpCodeName(TR_ARMOpCode *);
+   virtual const char * getOpCodeName(TR::InstOpCode *);
    const char * getName(TR::RealRegister *, TR_RegisterSizes size = TR_WordReg);
    const char * getName(uint32_t realRegisterIndex, TR_RegisterSizes = (TR_RegisterSizes)-1);
    void print(TR::FILE *, TR::ARMHelperCallSnippet *);