AArch64: Improve MemoryReference class for array access

Improve MemoryReference in aarch64 codegen. - Enable capturing aladd node in `populateMemoryReference` function. - Enable use of scale and extend code. - Simplify `consolidateRegisters` and `addToOffset` function. - Introduce `normalize` function to ensure invalid combination of base register and index register and offset is not used. Signed-off-by: Akira Saitoh <saiaki@jp.ibm.com>
eclipse · Dec 15, 2021 · 74f8db1 · 74f8db1
1 parent 5a958d7
commit 74f8db1
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Showing 6 changed files with 598 additions and 202 deletions.
diff --git a/compiler/aarch64/codegen/ARM64Debug.cpp b/compiler/aarch64/codegen/ARM64Debug.cpp
@@ -2005,7 +2005,23 @@ TR_Debug::print(TR::FILE *pOutFile, TR::MemoryReference *mr)
       }
 
    if (mr->getIndexRegister() != NULL)
+      {
       print(pOutFile, mr->getIndexRegister());
+      TR::ARM64ExtendCode extendCode = mr->getIndexExtendCode();
+      uint8_t scale = mr->getScale();
+
+      if ((extendCode != TR::ARM64ExtendCode::EXT_UXTX) || (scale != 0))
+         {
+         if (extendCode != TR::ARM64ExtendCode::EXT_UXTX)
+            {
+            trfprintf(pOutFile, ", %s %d", ARM64ExtendCodeNames[extendCode], scale);
+            }
+         else
+            {
+            trfprintf(pOutFile, ", lsl %d", scale);
+            }
+         }
+      }
    else
       trfprintf(pOutFile, "%d", mr->getOffset(true));
 

diff --git a/compiler/aarch64/codegen/ARM64Instruction.cpp b/compiler/aarch64/codegen/ARM64Instruction.cpp
@@ -457,7 +457,8 @@ TR::ARM64Trg1MemInstruction::ARM64Trg1MemInstruction(TR::InstOpCode::Mnemonic op
                            TR::Node *node,
                            TR::Register *treg,
                            TR::MemoryReference *mr, TR::CodeGenerator *cg)
-   : ARM64Trg1Instruction(op, node, treg, cg), _memoryReference(mr)
+   /* Choose a correct variant of the opcode for this memory reference. */
+   : ARM64Trg1Instruction(mr->mapOpCode(op), node, treg, cg), _memoryReference(mr)
    {
    mr->bookKeepingRegisterUses(self(), cg);
    TR::InstructionDelegate::setupImplicitNullPointerException(cg, this);
@@ -468,7 +469,8 @@ TR::ARM64Trg1MemInstruction::ARM64Trg1MemInstruction(TR::InstOpCode::Mnemonic op
                            TR::Register *treg,
                            TR::MemoryReference *mr,
                            TR::Instruction *precedingInstruction, TR::CodeGenerator *cg)
-   : ARM64Trg1Instruction(op, node, treg, precedingInstruction, cg), _memoryReference(mr)
+   /* Choose a correct variant of the opcode for this memory reference. */
+   : ARM64Trg1Instruction(mr->mapOpCode(op), node, treg, precedingInstruction, cg), _memoryReference(mr)
    {
    mr->bookKeepingRegisterUses(self(), cg);
    TR::InstructionDelegate::setupImplicitNullPointerException(cg, this);
@@ -520,7 +522,8 @@ void TR::ARM64Trg1MemInstruction::assignRegisters(TR_RegisterKinds kindToBeAssig
 TR::ARM64MemInstruction::ARM64MemInstruction(TR::InstOpCode::Mnemonic op,
                      TR::Node *node,
                      TR::MemoryReference *mr, TR::CodeGenerator *cg)
-   : TR::Instruction(op, node, cg), _memoryReference(mr)
+   /* Choose a correct variant of the opcode for this memory reference. */
+   : TR::Instruction(mr->mapOpCode(op), node, cg), _memoryReference(mr)
    {
    mr->bookKeepingRegisterUses(self(), cg);
    TR::InstructionDelegate::setupImplicitNullPointerException(cg, this);
@@ -530,7 +533,8 @@ TR::ARM64MemInstruction::ARM64MemInstruction(TR::InstOpCode::Mnemonic op,
                      TR::Node *node,
                      TR::MemoryReference *mr,
                      TR::Instruction *precedingInstruction, TR::CodeGenerator *cg)
-   : TR::Instruction(op, node, precedingInstruction, cg), _memoryReference(mr)
+   /* Choose a correct variant of the opcode for this memory reference. */
+   : TR::Instruction(mr->mapOpCode(op), node, precedingInstruction, cg), _memoryReference(mr)
    {
    mr->bookKeepingRegisterUses(self(), cg);
    TR::InstructionDelegate::setupImplicitNullPointerException(cg, this);

diff --git a/compiler/aarch64/codegen/ARM64Instruction.hpp b/compiler/aarch64/codegen/ARM64Instruction.hpp
@@ -96,7 +96,7 @@ inline bool constantIsImm7(int32_t intValue)
  * @param[in] intValue : signed integer value
  * @return true if the value can be placed in 9-bit field, false otherwise
  */
-inline bool constantIsImm9(int32_t intValue)
+inline bool constantIsImm9(int64_t intValue)
    {
    return (-256 <= intValue && intValue < 256);
    }

diff --git a/compiler/aarch64/codegen/GenerateInstructions.cpp b/compiler/aarch64/codegen/GenerateInstructions.cpp
@@ -265,7 +265,7 @@ TR::Instruction *generateTrg1Src2ShiftedInstruction(TR::CodeGenerator *cg, TR::I
    return new (cg->trHeapMemory()) TR::ARM64Trg1Src2ShiftedInstruction(op, node, treg, s1reg, s2reg, shiftType, shiftAmount, cg);
    }
 
-TR::Instruction *generateTrg1Src2ExtendtedInstruction(TR::CodeGenerator *cg, TR::InstOpCode::Mnemonic op, TR::Node *node,
+TR::Instruction *generateTrg1Src2ExtendedInstruction(TR::CodeGenerator *cg, TR::InstOpCode::Mnemonic op, TR::Node *node,
    TR::Register *treg, TR::Register *s1reg, TR::Register *s2reg,
    TR::ARM64ExtendCode extendType, uint32_t shiftAmount, TR::Instruction *preced)
    {