Skip to content

Commit

Permalink
Remove ARMOp_ prefix now that mnemonics are enum scoped
Browse files Browse the repository at this point in the history
  • Loading branch information
@fjeremic
fjeremic committed Jun 16, 2021
1 parent 8fc31ef commit 7fe991d
Show file tree
Hide file tree
Showing 20 changed files with 807 additions and 807 deletions.
26 changes: 13 additions & 13 deletions compiler/arm/codegen/ARMBinaryEncoding.cpp
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
Expand Down Expand Up @@ -255,7 +255,7 @@ uint8_t *TR::ARMImmSymInstruction::generateBinaryEncoding()
generateConditionBinaryEncoding(instructionStart);
TR::LabelSymbol *label;

if (getOpCodeValue() == TR::InstOpCode::ARMOp_bl)
if (getOpCodeValue() == TR::InstOpCode::bl)
{
label = getSymbolReference()->getSymbol()->getLabelSymbol();

Expand Down Expand Up @@ -339,7 +339,7 @@ uint8_t *TR::ARMImmSymInstruction::generateBinaryEncoding()
}
else
{
// Place holder only: non-TR::InstOpCode::ARMOp_bl usage of this instruction doesn't
// Place holder only: non-TR::InstOpCode::bl usage of this instruction doesn't
// exist at this moment.
TR_ASSERT(0, "non bl encoding");
int32_t distance = getSourceImmediate() - (intptr_t)cursor;
Expand Down Expand Up @@ -549,21 +549,21 @@ int32_t TR::ARMControlFlowInstruction::estimateBinaryLength(int32_t currentEstim
{
switch(getOpCodeValue())
{
case TR::InstOpCode::ARMOp_iflong:
case TR::InstOpCode::ARMOp_setbool:
case TR::InstOpCode::iflong:
case TR::InstOpCode::setbool:
setEstimatedBinaryLength(ARM_INSTRUCTION_LENGTH * 4);
break;
case TR::InstOpCode::ARMOp_idiv:
case TR::InstOpCode::ARMOp_setbflt:
case TR::InstOpCode::idiv:
case TR::InstOpCode::setbflt:
setEstimatedBinaryLength(ARM_INSTRUCTION_LENGTH * 5);
break;
case TR::InstOpCode::ARMOp_setblong:
case TR::InstOpCode::ARMOp_flcmpg:
case TR::InstOpCode::ARMOp_flcmpl:
case TR::InstOpCode::ARMOp_irem:
case TR::InstOpCode::setblong:
case TR::InstOpCode::flcmpg:
case TR::InstOpCode::flcmpl:
case TR::InstOpCode::irem:
setEstimatedBinaryLength(ARM_INSTRUCTION_LENGTH * 6);
break;
case TR::InstOpCode::ARMOp_lcmp:
case TR::InstOpCode::lcmp:
setEstimatedBinaryLength(ARM_INSTRUCTION_LENGTH * 5);
break;
}
Expand Down Expand Up @@ -624,7 +624,7 @@ uint8_t *TR::ARMVirtualGuardNOPInstruction::generateBinaryEncoding()
// 2) We might want to re-enable the code path and unpatch, in which case we would have to know what the old instruction was
cg()->comp()->compileRelocatableCode())
{
TR::InstOpCode opCode(TR::InstOpCode::ARMOp_nop);
TR::InstOpCode opCode(TR::InstOpCode::nop);
opCode.copyBinaryToBuffer(cursor);
length = ARM_INSTRUCTION_LENGTH;
}
Expand Down
42 changes: 21 additions & 21 deletions compiler/arm/codegen/ARMDebug.cpp
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (c) 2000, 2020 IBM Corp. and others
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
Expand Down Expand Up @@ -136,7 +136,7 @@ static const char * opCodeToVFPMap[] =
static const char *
getExtraVFPInstrSpecifiers(TR::InstOpCode *opCode)
{
#define FIRST_VFP_INSTR TR::InstOpCode::ARMOp_fabsd
#define FIRST_VFP_INSTR TR::InstOpCode::fabsd

#if defined(__ARM_ARCH_7A__) && defined(__VFP_FP__) && !defined(__SOFTFP__)
uint32_t index = (uint32_t)opCode->getOpCodeValue() - (uint32_t)(FIRST_VFP_INSTR);
Expand Down Expand Up @@ -326,7 +326,7 @@ TR_Debug::print(TR::FILE *pOutFile, TR::ARMLabelInstruction * instr)
else if (label->isEndInternalControlFlow())
trfprintf(pOutFile, " (End of internal control flow)");
}
else if (instr->getOpCodeValue() == TR::InstOpCode::ARMOp_b || instr->getOpCodeValue() == TR::InstOpCode::ARMOp_bl)
else if (instr->getOpCodeValue() == TR::InstOpCode::b || instr->getOpCodeValue() == TR::InstOpCode::bl)
{
trfprintf(pOutFile, "%s\t", fullOpCodeName(instr));
print(pOutFile, label);
Expand Down Expand Up @@ -488,7 +488,7 @@ TR_Debug::print(TR::FILE *pOutFile, TR::ARMTrg1Src2Instruction * instr)
printPrefix(pOutFile, instr);
trfprintf(pOutFile, "%s\t", fullOpCodeName(instr));
#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
if (instr->getOpCodeValue() == TR::InstOpCode::ARMOp_fmrs)
if (instr->getOpCodeValue() == TR::InstOpCode::fmrs)
{
if (instr->getTarget1Register())
{
Expand All @@ -500,7 +500,7 @@ TR_Debug::print(TR::FILE *pOutFile, TR::ARMTrg1Src2Instruction * instr)
print(pOutFile, instr->getSource1Register(), source1Size);
}
}
else if (instr->getOpCodeValue() == TR::InstOpCode::ARMOp_fmsr)
else if (instr->getOpCodeValue() == TR::InstOpCode::fmsr)
{
if (instr->getSource1Register())
{
Expand All @@ -512,34 +512,34 @@ TR_Debug::print(TR::FILE *pOutFile, TR::ARMTrg1Src2Instruction * instr)
print(pOutFile, instr->getTarget1Register(), targetSize);
}
}
else if (instr->getOpCodeValue() == TR::InstOpCode::ARMOp_fmdrr)
else if (instr->getOpCodeValue() == TR::InstOpCode::fmdrr)
{
print(pOutFile, instr->getSource2Operand(), TR_DoubleReg);
trfprintf(pOutFile, ", ");
print(pOutFile, instr->getTarget1Register(), TR_WordReg);
trfprintf(pOutFile, ", ");
print(pOutFile, instr->getSource1Register(), TR_WordReg);
}
else if (instr->getOpCodeValue() == TR::InstOpCode::ARMOp_fcvtds ||
instr->getOpCodeValue() == TR::InstOpCode::ARMOp_fsitod ||
instr->getOpCodeValue() == TR::InstOpCode::ARMOp_fuitod)
else if (instr->getOpCodeValue() == TR::InstOpCode::fcvtds ||
instr->getOpCodeValue() == TR::InstOpCode::fsitod ||
instr->getOpCodeValue() == TR::InstOpCode::fuitod)
{
print(pOutFile, instr->getTarget1Register(), TR_DoubleReg);
trfprintf(pOutFile, ", ");
print(pOutFile, instr->getSource2Operand(), TR_WordReg);
}
else if (instr->getOpCodeValue() == TR::InstOpCode::ARMOp_fcvtsd ||
instr->getOpCodeValue() == TR::InstOpCode::ARMOp_ftosizd ||
instr->getOpCodeValue() == TR::InstOpCode::ARMOp_ftouizd)
else if (instr->getOpCodeValue() == TR::InstOpCode::fcvtsd ||
instr->getOpCodeValue() == TR::InstOpCode::ftosizd ||
instr->getOpCodeValue() == TR::InstOpCode::ftouizd)
{
print(pOutFile, instr->getTarget1Register(), TR_WordReg);
trfprintf(pOutFile, ", ");
print(pOutFile, instr->getSource2Operand(), TR_DoubleReg);
}
else if (instr->getOpCodeValue() == TR::InstOpCode::ARMOp_fcmpzd ||
instr->getOpCodeValue() == TR::InstOpCode::ARMOp_fcmpzs)
else if (instr->getOpCodeValue() == TR::InstOpCode::fcmpzd ||
instr->getOpCodeValue() == TR::InstOpCode::fcmpzs)
{
print(pOutFile, instr->getTarget1Register(), (instr->getOpCodeValue() == TR::InstOpCode::ARMOp_fcmpzd) ? TR_DoubleReg : TR_WordReg);
print(pOutFile, instr->getTarget1Register(), (instr->getOpCodeValue() == TR::InstOpCode::fcmpzd) ? TR_DoubleReg : TR_WordReg);
#if defined(__ARM_ARCH_7A__) && defined(__VFP_FP__) && !defined(__SOFTFP__)
trfprintf(pOutFile, ", #0.0");
#endif
Expand All @@ -554,14 +554,14 @@ TR_Debug::print(TR::FILE *pOutFile, TR::ARMTrg1Src2Instruction * instr)
trfprintf(pOutFile, ", ");
}
// TR_RegisterSizes source1Size = TR_WordReg;
if (instr->getSource1Register() && instr->getOpCodeValue() != TR::InstOpCode::ARMOp_swp)
if (instr->getSource1Register() && instr->getOpCodeValue() != TR::InstOpCode::swp)
{
print(pOutFile, instr->getSource1Register(), source1Size);
trfprintf(pOutFile, ", ");
}
// TR_RegisterSizes source2Size = TR_WordReg;
print(pOutFile, instr->getSource2Operand(), source2Size);
if (instr->getSource1Register() && instr->getOpCodeValue() == TR::InstOpCode::ARMOp_swp)
if (instr->getSource1Register() && instr->getOpCodeValue() == TR::InstOpCode::swp)
{
trfprintf(pOutFile, ", [");
print(pOutFile, instr->getSource1Register(), source1Size);
Expand Down Expand Up @@ -630,7 +630,7 @@ TR_Debug::print(TR::FILE *pOutFile, TR::ARMMemSrc1Instruction * instr)
{
TR::InstOpCode::Mnemonic op = instr->getOpCodeValue();
int32_t offset = instr->getMemoryReference()->getOffset();
if(op == TR::InstOpCode::ARMOp_strh && !constantIsUnsignedImmed8(offset))
if(op == TR::InstOpCode::strh && !constantIsUnsignedImmed8(offset))
{
printARMDelayedOffsetInstructions(pOutFile,instr);
return;
Expand Down Expand Up @@ -685,12 +685,12 @@ TR_Debug::print(TR::FILE *pOutFile, TR::ARMTrg1MemInstruction * instr)
{
TR::InstOpCode::Mnemonic op = instr->getOpCodeValue();
int32_t offset = instr->getMemoryReference()->getOffset();
if(op == TR::InstOpCode::ARMOp_add && instr->getMemoryReference()->getIndexRegister())
if(op == TR::InstOpCode::add && instr->getMemoryReference()->getIndexRegister())
{
printARMDelayedOffsetInstructions(pOutFile,instr);
return;
}
else if((op == TR::InstOpCode::ARMOp_ldrsb || op == TR::InstOpCode::ARMOp_ldrh || op == TR::InstOpCode::ARMOp_ldrsh) && !constantIsUnsignedImmed8(offset))
else if((op == TR::InstOpCode::ldrsb || op == TR::InstOpCode::ldrh || op == TR::InstOpCode::ldrsh) && !constantIsUnsignedImmed8(offset))
{
printARMDelayedOffsetInstructions(pOutFile,instr);
return;
Expand Down Expand Up @@ -1536,7 +1536,7 @@ TR_Debug::printARMDelayedOffsetInstructions(TR::FILE *pOutFile, TR::ARMMemInstru
char *regName = (char *)_comp->trMemory()->allocateHeapMemory(6);
sprintf(regName,"gr%d",(*(uint32_t *)bufferPos >> TR::RealRegister::pos_RD) & 0xf);

if(op == TR::InstOpCode::ARMOp_str || op == TR::InstOpCode::ARMOp_strh || op == TR::InstOpCode::ARMOp_strb ||
if(op == TR::InstOpCode::str || op == TR::InstOpCode::strh || op == TR::InstOpCode::strb ||
toRealRegister(instr->getMemoryDataRegister())->getRegisterNumber() == base->getRegisterNumber())
{
regSpilled = true;
Expand Down
30 changes: 15 additions & 15 deletions compiler/arm/codegen/ARMGenerateInstructions.cpp
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (c) 2000, 2016 IBM Corp. and others
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
Expand Down Expand Up @@ -272,13 +272,13 @@ TR::Instruction *generateTrg1Src1Instruction(TR::CodeGenerator *cg,
TR::Register *s1reg,
TR::Instruction *prev)
{
if (op == TR::InstOpCode::ARMOp_fmrs || op == TR::InstOpCode::ARMOp_fmsr)
if (op == TR::InstOpCode::fmrs || op == TR::InstOpCode::fmsr)
{
TR_ARMOperand2 *operand = new (cg->trHeapMemory()) TR_ARMOperand2(0, 0);
if (prev)
return new (cg->trHeapMemory()) TR::ARMTrg1Src2Instruction(prev, op, node, (op==TR::InstOpCode::ARMOp_fmrs)?treg:s1reg, (op==TR::InstOpCode::ARMOp_fmrs)?s1reg:treg, operand, cg);
return new (cg->trHeapMemory()) TR::ARMTrg1Src2Instruction(prev, op, node, (op==TR::InstOpCode::fmrs)?treg:s1reg, (op==TR::InstOpCode::fmrs)?s1reg:treg, operand, cg);
else
return new (cg->trHeapMemory()) TR::ARMTrg1Src2Instruction(op, node, (op==TR::InstOpCode::ARMOp_fmrs)?treg:s1reg, (op==TR::InstOpCode::ARMOp_fmrs)?s1reg:treg, operand, cg);
return new (cg->trHeapMemory()) TR::ARMTrg1Src2Instruction(op, node, (op==TR::InstOpCode::fmrs)?treg:s1reg, (op==TR::InstOpCode::fmrs)?s1reg:treg, operand, cg);
}
else
{
Expand Down Expand Up @@ -340,7 +340,7 @@ TR::Instruction *generateTrg1Src2Instruction(TR::CodeGenerator *cg,
TR::Register *s2reg,
TR::Instruction *prev)
{
if (op == TR::InstOpCode::ARMOp_fmdrr)
if (op == TR::InstOpCode::fmdrr)
{
// fmdrr Dm, Rd, Rn
TR_ARMOperand2 *toperand = new (cg->trHeapMemory()) TR_ARMOperand2(ARMOp2Reg, treg);
Expand Down Expand Up @@ -413,7 +413,7 @@ TR::Instruction *generateShiftLeftImmediate(TR::CodeGenerator *cg,
TR::Instruction *prev)
{
TR_ARMOperand2 *operand = new (cg->trHeapMemory()) TR_ARMOperand2(type, srcReg, shiftAmount);
return generateTrg1Src1Instruction(cg, TR::InstOpCode::ARMOp_mov, node, trgReg, operand, prev);
return generateTrg1Src1Instruction(cg, TR::InstOpCode::mov, node, trgReg, operand, prev);
}

TR::Instruction *generateShiftLeftByRegister(TR::CodeGenerator *cg,
Expand All @@ -424,7 +424,7 @@ TR::Instruction *generateShiftLeftByRegister(TR::CodeGenerator *cg,
TR::Instruction *prev)
{
TR_ARMOperand2 *operand = new (cg->trHeapMemory()) TR_ARMOperand2(ARMOp2RegLSLReg, srcReg, shiftRegister);
return generateTrg1Src1Instruction(cg, TR::InstOpCode::ARMOp_mov, node, trgReg, operand, prev);
return generateTrg1Src1Instruction(cg, TR::InstOpCode::mov, node, trgReg, operand, prev);
}

TR::Instruction *generateShiftRightImmediate(TR::CodeGenerator *cg,
Expand All @@ -437,7 +437,7 @@ TR::Instruction *generateShiftRightImmediate(TR::CodeGenerator *cg,
{
TR_ARMOperand2Type type = (isLogical == true ? ARMOp2RegLSRImmed : ARMOp2RegASRImmed);
TR_ARMOperand2 *operand = new (cg->trHeapMemory()) TR_ARMOperand2(type, srcReg, shiftAmount);
return generateTrg1Src1Instruction(cg, TR::InstOpCode::ARMOp_mov, node, trgReg, operand, prev);
return generateTrg1Src1Instruction(cg, TR::InstOpCode::mov, node, trgReg, operand, prev);
}

TR::Instruction *generateShiftRightByRegister(TR::CodeGenerator *cg,
Expand All @@ -450,7 +450,7 @@ TR::Instruction *generateShiftRightByRegister(TR::CodeGenerator *cg,
{
TR_ARMOperand2Type type = (isLogical == true ? ARMOp2RegLSRReg : ARMOp2RegASRReg);
TR_ARMOperand2 *operand = new (cg->trHeapMemory()) TR_ARMOperand2(type, srcReg, shiftRegister);
return generateTrg1Src1Instruction(cg, TR::InstOpCode::ARMOp_mov, node, trgReg, operand, prev);
return generateTrg1Src1Instruction(cg, TR::InstOpCode::mov, node, trgReg, operand, prev);
}

TR::Instruction *generateLabelInstruction(TR::CodeGenerator *cg,
Expand Down Expand Up @@ -487,9 +487,9 @@ TR::Instruction *generateConditionalBranchInstruction(TR::CodeGenerator *cg,
TR::Instruction *prev)
{
if (prev)
return new (cg->trHeapMemory()) TR::ARMConditionalBranchInstruction(prev, TR::InstOpCode::ARMOp_b, node, sym, cc, cg);
return new (cg->trHeapMemory()) TR::ARMConditionalBranchInstruction(prev, TR::InstOpCode::b, node, sym, cc, cg);
else
return new (cg->trHeapMemory()) TR::ARMConditionalBranchInstruction(TR::InstOpCode::ARMOp_b, node, sym, cc, cg);
return new (cg->trHeapMemory()) TR::ARMConditionalBranchInstruction(TR::InstOpCode::b, node, sym, cc, cg);
}

TR::Instruction *generateConditionalBranchInstruction(TR::CodeGenerator *cg,
Expand All @@ -500,9 +500,9 @@ TR::Instruction *generateConditionalBranchInstruction(TR::CodeGenerator
TR::Instruction *prev)
{
if (prev)
return new (cg->trHeapMemory()) TR::ARMConditionalBranchInstruction(prev, TR::InstOpCode::ARMOp_b, node, cond, sym, cc, cg);
return new (cg->trHeapMemory()) TR::ARMConditionalBranchInstruction(prev, TR::InstOpCode::b, node, cond, sym, cc, cg);
else
return new (cg->trHeapMemory()) TR::ARMConditionalBranchInstruction(TR::InstOpCode::ARMOp_b, node, cond, sym, cc, cg);
return new (cg->trHeapMemory()) TR::ARMConditionalBranchInstruction(TR::InstOpCode::b, node, cond, sym, cc, cg);
}

TR::ARMControlFlowInstruction *generateControlFlowInstruction(TR::CodeGenerator *cg,
Expand All @@ -526,9 +526,9 @@ TR::Instruction *generatePreIncLoadInstruction(TR::CodeGenerator *cg,
TR::MemoryReference *updateMR = new (cg->trHeapMemory()) TR::MemoryReference(baseReg, offset, cg);
updateMR->setImmediatePreIndexed(); // write the updated EA back into baseReg
if (prev)
return new (cg->trHeapMemory()) TR::ARMTrg1MemInstruction(prev, TR::InstOpCode::ARMOp_ldr, node, treg, updateMR, cg);
return new (cg->trHeapMemory()) TR::ARMTrg1MemInstruction(prev, TR::InstOpCode::ldr, node, treg, updateMR, cg);
else
return new (cg->trHeapMemory()) TR::ARMTrg1MemInstruction(TR::InstOpCode::ARMOp_ldr, node, treg, updateMR, cg);
return new (cg->trHeapMemory()) TR::ARMTrg1MemInstruction(TR::InstOpCode::ldr, node, treg, updateMR, cg);
}

#ifdef J9_PROJECT_SPECIFIC
Expand Down
6 changes: 3 additions & 3 deletions compiler/arm/codegen/ARMInstruction.hpp
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (c) 2000, 2018 IBM Corp. and others
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
Expand Down Expand Up @@ -700,7 +700,7 @@ class ARMLoadStartPCInstruction : public TR::ARMTrg1Src2Instruction
TR::Register *treg,
TR::SymbolReference *symRef,
TR::CodeGenerator *cg)
: TR::ARMTrg1Src2Instruction(TR::InstOpCode::ARMOp_sub, node, treg, cg->machine()->getRealRegister(TR::RealRegister::gr15),
: TR::ARMTrg1Src2Instruction(TR::InstOpCode::sub, node, treg, cg->machine()->getRealRegister(TR::RealRegister::gr15),
new (cg->trHeapMemory()) TR_ARMOperand2(0xde, 24), cg), /* The value 0xde does not mean anything. It will be replaced in the binary encoding phase. */
_symbolReference(symRef)
{
Expand All @@ -711,7 +711,7 @@ class ARMLoadStartPCInstruction : public TR::ARMTrg1Src2Instruction
TR::Register *treg,
TR::SymbolReference *symRef,
TR::CodeGenerator *cg)
: TR::ARMTrg1Src2Instruction(precedingInstruction, TR::InstOpCode::ARMOp_sub, node, treg, cg->machine()->getRealRegister(TR::RealRegister::gr15),
: TR::ARMTrg1Src2Instruction(precedingInstruction, TR::InstOpCode::sub, node, treg, cg->machine()->getRealRegister(TR::RealRegister::gr15),
new (cg->trHeapMemory()) TR_ARMOperand2(0xde, 0), cg), /* The value 0xde does not mean anything. It will be replaced in the binary encoding phase. */
_symbolReference(symRef)
{
Expand Down
6 changes: 3 additions & 3 deletions compiler/arm/codegen/ARMOutOfLineCodeSection.cpp
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (c) 2000, 2018 IBM Corp. and others
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
Expand Down Expand Up @@ -54,12 +54,12 @@ void TR_ARMOutOfLineCodeSection::generateARMOutOfLineCodeSectionDispatch()
if (_targetReg)
{
TR_ASSERT(resultReg, "assertion failure");
generateTrg1Src1Instruction(_cg, TR::InstOpCode::ARMOp_mov, _callNode, _targetReg, resultReg);
generateTrg1Src1Instruction(_cg, TR::InstOpCode::mov, _callNode, _targetReg, resultReg);
}
_cg->decReferenceCount(_callNode);

if (_restartLabel)
generateLabelInstruction(_cg, TR::InstOpCode::ARMOp_b, _callNode, _restartLabel);
generateLabelInstruction(_cg, TR::InstOpCode::b, _callNode, _restartLabel);

generateLabelInstruction(_cg, TR::InstOpCode::label, _callNode, generateLabelSymbol(_cg));

Expand Down
Loading

0 comments on commit 7fe991d

Please sign in to comment.