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Implement vmul for type ByteVector of size 128
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Signed-off-by: midronij <jackie.midroni@ibm.com>
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@midronij
midronij committed Nov 26, 2021
1 parent 5f7c29a commit 844927e
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Showing 5 changed files with 74 additions and 31 deletions.
6 changes: 2 additions & 4 deletions compiler/p/codegen/OMRCodeGenerator.cpp
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Expand Up @@ -1774,13 +1774,11 @@ bool OMR::Power::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode
{
case TR::vadd:
case TR::vsub:
if (dt == TR::Int16 || dt == TR::Int8 || dt == TR::Int32 || dt == TR::Float || dt == TR::Double)
case TR::vmul:
if (dt == TR::Int8 || dt == TR::Int16 || dt == TR::Int32 || dt == TR::Float || dt == TR::Double)
return true;
else
return false;
case TR::vmul:
if (dt == TR::Int16)
return true;
case TR::vdiv:
case TR::vneg:
if (dt == TR::Int32 || dt == TR::Float || dt == TR::Double)
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4 changes: 2 additions & 2 deletions compiler/p/codegen/OMRInstOpCode.enum
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Expand Up @@ -718,10 +718,10 @@
// vmsumubm, // Vector Multiply-Sum Unsigned Byte Modulo
// vmsumuhs, // Vector Multiply-Sum Unsigned Hword Saturate
// vmulesb, // Vector Multiply Even Signed Byte
// vmuleub, // Vector Multiply Even Unsigned Byte
vmuleub, // Vector Multiply Even Unsigned Byte
// vmuleuh, // Vector Multiply Even Unsigned Hword
// vmulosb, // Vector Multiply Odd Signed Byte
// vmuloub, // Vector Multiply Odd Unsigned Byte
vmuloub, // Vector Multiply Odd Unsigned Byte
vmulesh, // vector multiply even signed halfword
vmulosh, // vector multiply odd signed halfword
vmulouh, // vector multiply odd unsigned halfword
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42 changes: 21 additions & 21 deletions compiler/p/codegen/OMRInstOpCodeProperties.hpp
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Expand Up @@ -8361,7 +8361,7 @@
/* .opcode = */ 0x10000022,
/* .format = */ FORMAT_VRT_VRA_VRB_VRC,
/* .minimumALS = */ OMR_PROCESSOR_PPC_P6,
/* .properties = */ PPCOpProp_IsVMX |
/* .properties = */ PPCOpProp_IsVMX |
PPCOpProp_SyncSideEffectFree,
},

Expand Down Expand Up @@ -8437,17 +8437,17 @@
/* PPCOpProp_SyncSideEffectFree, */
/* }, */

/* { */
/* .mnemonic = OMR::InstOpCode::vmuleub, */
/* .name = "vmuleub", */
{
/* .mnemonic = */ OMR::InstOpCode::vmuleub,
/* .name = */ "vmuleub",
/* .description = "Vector Multiply Even Unsigned Byte", */
/* .prefix = 0x00000000, */
/* .opcode = 0x10000208, */
/* .format = FORMAT_UNKNOWN, */
/* .minimumALS = OMR_PROCESSOR_PPC_P6, */
/* .properties = PPCOpProp_IsVMX | */
/* PPCOpProp_SyncSideEffectFree, */
/* }, */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x10000208,
/* .format = */ FORMAT_VRT_VRA_VRB,
/* .minimumALS = */ OMR_PROCESSOR_PPC_P6,
/* .properties = */ PPCOpProp_IsVMX |
PPCOpProp_SyncSideEffectFree,
},

/* { */
/* .mnemonic = OMR::InstOpCode::vmuleuh, */
Expand All @@ -8473,17 +8473,17 @@
/* PPCOpProp_SyncSideEffectFree, */
/* }, */

/* { */
/* .mnemonic = OMR::InstOpCode::vmuloub, */
/* .name = "vmuloub", */
{
/* .mnemonic = */ OMR::InstOpCode::vmuloub,
/* .name = */ "vmuloub",
/* .description = "Vector Multiply Odd Unsigned Byte", */
/* .prefix = 0x00000000, */
/* .opcode = 0x10000008, */
/* .format = FORMAT_UNKNOWN, */
/* .minimumALS = OMR_PROCESSOR_PPC_P6, */
/* .properties = PPCOpProp_IsVMX | */
/* PPCOpProp_SyncSideEffectFree, */
/* }, */
/* .prefix = */ 0x00000000,
/* .opcode = */ 0x10000008,
/* .format = */ FORMAT_VRT_VRA_VRB,
/* .minimumALS = */ OMR_PROCESSOR_PPC_P6,
/* .properties = */ PPCOpProp_IsVMX |
PPCOpProp_SyncSideEffectFree,
},

{
/* .mnemonic = */ OMR::InstOpCode::vmulesh,
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52 changes: 48 additions & 4 deletions compiler/p/codegen/OMRTreeEvaluator.cpp
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Expand Up @@ -3460,19 +3460,65 @@ TR::Register *OMR::Power::TreeEvaluator::vmulEvaluator(TR::Node *node, TR::CodeG
{
switch(node->getDataType())
{
case TR::VectorInt8:
return TR::TreeEvaluator::vmulInt8Helper(node, cg);
case TR::VectorInt16:
return TR::TreeEvaluator::vmulInt16Helper(node,cg);
case TR::VectorInt32:
return TR::TreeEvaluator::vmulInt32Helper(node,cg);
case TR::VectorFloat:
return TR::TreeEvaluator::vmulFloatHelper(node,cg);
case TR::VectorDouble:
return TR::TreeEvaluator::vmulDoubleHelper(node,cg);
case TR::VectorInt16:
return TR::TreeEvaluator::vmulInt16Helper(node,cg);
default:
TR_ASSERT(false, "unrecognized vector type %s\n", node->getDataType().toString()); return NULL;
}
}

TR::Register *OMR::Power::TreeEvaluator::vmulInt8Helper(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild;
TR::Node *secondChild;
TR::Register *lhsReg, *rhsReg;
TR::Register *productReg;
TR::Register *temp;
TR::Register *shiftReg;

firstChild = node->getFirstChild();
secondChild = node->getSecondChild();

lhsReg = cg->evaluate(firstChild);
rhsReg = cg->evaluate(secondChild);

productReg = cg->allocateRegister(TR_VRF);
temp = cg->allocateRegister(TR_VRF);
shiftReg = cg->allocateRegister(TR_VRF);

node->setRegister(productReg);

//set shift amount to 1 byte
generateTrg1ImmInstruction(cg, TR::InstOpCode::vspltisb, node, shiftReg, 8);

//multiply even bytes and shift to correct location
generateTrg1Src2Instruction(cg, TR::InstOpCode::vmuleub, node, productReg, lhsReg, rhsReg);
generateTrg1Src2Instruction(cg, TR::InstOpCode::vslh, node, productReg, productReg, shiftReg);

//multiply odd byte and shift left (to discard upper byte of product) and then right (to relocate to correct position)
generateTrg1Src2Instruction(cg, TR::InstOpCode::vmuloub, node, temp, lhsReg, rhsReg);
generateTrg1Src2Instruction(cg, TR::InstOpCode::vslh, node, temp, temp, shiftReg);
generateTrg1Src2Instruction(cg, TR::InstOpCode::vsrh, node, temp, temp, shiftReg);

//add odd and even bytes together to get full vector of products
generateTrg1Src2Instruction(cg, TR::InstOpCode::vaddubm, node, productReg, productReg, temp);

cg->stopUsingRegister(temp);
cg->stopUsingRegister(shiftReg);
cg->decReferenceCount(firstChild);
cg->decReferenceCount(secondChild);

return productReg;
}

TR::Register *OMR::Power::TreeEvaluator::vmulInt16Helper(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *firstChild;
Expand All @@ -3483,8 +3529,6 @@ TR::Register *OMR::Power::TreeEvaluator::vmulInt16Helper(TR::Node *node, TR::Cod

firstChild = node->getFirstChild();
secondChild = node->getSecondChild();
lhsReg = NULL;
rhsReg = NULL;

lhsReg = cg->evaluate(firstChild);
rhsReg = cg->evaluate(secondChild);
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1 change: 1 addition & 0 deletions compiler/p/codegen/OMRTreeEvaluator.hpp
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Expand Up @@ -638,6 +638,7 @@ class OMR_EXTENSIBLE TreeEvaluator: public OMR::TreeEvaluator
static TR::Register *vaddEvaluator(TR::Node *node, TR::CodeGenerator *cg);
static TR::Register *vsubEvaluator(TR::Node *node, TR::CodeGenerator *cg);
static TR::Register *vmulEvaluator(TR::Node *node, TR::CodeGenerator *cg);
static TR::Register *vmulInt8Helper(TR::Node *node, TR::CodeGenerator *cg);
static TR::Register *vmulInt16Helper(TR::Node *node, TR::CodeGenerator *cg);
static TR::Register *vmulInt32Helper(TR::Node *node, TR::CodeGenerator *cg);
static TR::Register *vmulFloatHelper(TR::Node *node, TR::CodeGenerator *cg);
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