Remove restriction on HPRs for Linux on Z 31-bit

On Linux on Z 31-bit JVMs we should still be able to allocate HPRs
without a problem. This was a historical artifact left from when HPRs
were not properly being preserved on 31-bit.

Signed-off-by: Filip Jeremic <fjeremic@ca.ibm.com>

compiler/codegen/CodeGenRA.cpp

@@ -1151,7 +1151,6 @@ OMR::CodeGenerator::pickRegister(TR_RegisterCandidate     *rc,
                                TR_GlobalRegisterNumber & highRegisterNumber,
                                TR_LinkHead<TR_RegisterCandidate> *candidatesAlreadyAssigned)
    {
-   bool enableHighWordGRA =  self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_DisableHighWordRA);
    static volatile bool isInitialized=false;
    static volatile uint8_t gprsWithheldFromPickRegister=0, fprsWithheldFromPickRegister=0, vrfWithheldFromPickRegister=0, gprsWithheldFromPickRegisterWhenWarm=0;
    int32_t currentCandidateWeight =-1;
@@ -1390,7 +1389,7 @@ OMR::CodeGenerator::pickRegister(TR_RegisterCandidate     *rc,
                   // Perform the simulation for current block and accumulate into highWaterMark
                   //
                   TR_RegisterPressureSummary summary(state._gprPressure, state._fprPressure, state._vrfPressure);
-                  if (enableHighWordGRA)
+                  if (self()->supportsHighWordFacility())
                      {
                      TR::DataType dtype = rc->getSymbolReference()->getSymbol()->getDataType();
                      if (dtype == TR::Int8 ||
@@ -1700,7 +1699,7 @@ OMR::CodeGenerator::pickRegister(TR_RegisterCandidate     *rc,
             }
          }
 
-      if (enableHighWordGRA)
+      if (self()->supportsHighWordFacility())
          {
          TR_BitVector HPRMasks = *self()->getGlobalRegisters(TR_hprSpill, self()->comp()->getMethodSymbol()->getLinkageConvention());
          // We cannot assign an HPR if the corresponding GPR is alive.
@@ -2575,7 +2574,6 @@ nodeGotFoldedIntoMemref(
 void
 OMR::CodeGenerator::simulateTreeEvaluation(TR::Node *node, TR_RegisterPressureState *state, TR_RegisterPressureSummary *summary)
    {
-   bool enableHighWordGRA = self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_DisableHighWordRA);
    // Analogous to cg->evaluate(node).
    //
    // This can be called on nodes that have already been evaluated, and it does
@@ -2638,7 +2636,7 @@ OMR::CodeGenerator::simulateTreeEvaluation(TR::Node *node, TR_RegisterPressureSt
       return;
       }
 
-   if (enableHighWordGRA)
+   if (self()->supportsHighWordFacility())
       {
       // 390 Highword, maybe move this below to else .hasRegister?
       if (self()->isCandidateLoad(node, state))
@@ -2763,7 +2761,7 @@ OMR::CodeGenerator::simulateTreeEvaluation(TR::Node *node, TR_RegisterPressureSt
                traceMsg(self()->comp(), " ++%s", self()->getDebug()->getName(child));
             }
 
-         if (enableHighWordGRA)
+         if (self()->supportsHighWordFacility())
             {
             // first time visiting this node, clear the flag
             if (node->getVisitCount() == state->_visitCountForInit && !self()->isCandidateLoad(node, state))
@@ -2773,7 +2771,7 @@ OMR::CodeGenerator::simulateTreeEvaluation(TR::Node *node, TR_RegisterPressureSt
             }
          self()->simulateNodeEvaluation(node, state, summary);
 
-         if (enableHighWordGRA)
+         if (self()->supportsHighWordFacility())
             {
             bool needToCheckHPR = false;
             for (uint16_t i = 0; i < node->getNumChildren(); i++)
@@ -2812,7 +2810,7 @@ OMR::CodeGenerator::simulateTreeEvaluation(TR::Node *node, TR_RegisterPressureSt
          }
       else
          {
-         if (enableHighWordGRA)
+         if (self()->supportsHighWordFacility())
             {
             // first time visiting this node, clear the flag
             if (node->getVisitCount() == state->_visitCountForInit && !self()->isCandidateLoad(node, state))
@@ -2841,7 +2839,7 @@ OMR::CodeGenerator::simulateTreeEvaluation(TR::Node *node, TR_RegisterPressureSt
 
          self()->simulateNodeEvaluation(node, state, summary);
 
-         if (enableHighWordGRA)
+         if (self()->supportsHighWordFacility())
             {
             bool needToCheckHPR = false;
             for (uint16_t i = 0; i < node->getNumChildren(); i++)

compiler/codegen/OMRCodeGenerator.cpp

@@ -1138,7 +1138,7 @@ OMR::CodeGenerator::getNumberOfGlobalRegisters()
 #ifdef TR_HOST_S390
 uint16_t OMR::CodeGenerator::getNumberOfGlobalGPRs()
    {
-   if (self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_DisableHighWordRA))
+   if (self()->supportsHighWordFacility())
       {
       return _firstGlobalHPR;
       }

compiler/optimizer/RegisterCandidate.cpp

@@ -2852,7 +2852,7 @@ TR_RegisterCandidates::assign(TR::Block ** cfgBlocks, int32_t numberOfBlocks, in
       TR::CodeGenerator * cg = comp()->cg();
       cg->removeUnavailableRegisters(rc, blocks, availableRegisters);
 
-      if (comp()->cg()->supportsHighWordFacility() && !comp()->getOption(TR_DisableHighWordRA) && !comp()->getOption(TR_DisableRegisterPressureSimulation))
+      if (comp()->cg()->supportsHighWordFacility() && !comp()->getOption(TR_DisableRegisterPressureSimulation))
          {
          if (!rc->getType().isInt8() && !rc->getType().isInt16() && !rc->getType().isInt32())
             {

compiler/z/codegen/BinaryAnalyser.hpp

@@ -65,7 +65,7 @@ class TR_S390BinaryAnalyser : public TR_Analyser
      {
 
      TR::InstOpCode::Mnemonic loadOp = TR::InstOpCode::getLoadRegOpCode();
-     if (cg()->supportsHighWordFacility() && !cg()->comp()->getOption(TR_DisableHighWordRA))
+     if (cg()->supportsHighWordFacility())
         {
         loadOp = TR::InstOpCode::LR;
         }

compiler/z/codegen/BinaryEvaluator.cpp

@@ -1303,7 +1303,7 @@ genericIntShift(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpCode::Mnemoni
          {
          if (trgReg != srcReg && canUseAltShiftOp )
             {
-            if (cg->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA) && srcReg->assignToHPR() &&
+            if (cg->supportsHighWordFacility() && srcReg->assignToHPR() &&
                 (altShiftOp == TR::InstOpCode::SLLK || altShiftOp == TR::InstOpCode::SRLK ))
                {
                if (altShiftOp == TR::InstOpCode::SLLK)
@@ -1632,7 +1632,7 @@ genericRotateAndInsertHelper(TR::Node * node, TR::CodeGenerator * cg)
          {
          // if GRA had decided to assign HPR to these nodes, we cannot use RISBG because they are 64-bit
          // instructions
-         if (cg->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA) &&
+         if (cg->supportsHighWordFacility() &&
              firstChild->getFirstChild()->getRegister() &&
              firstChild->getFirstChild()->getRegister()->assignToHPR())
             {

compiler/z/codegen/OMRCodeGenerator.cpp

@@ -606,12 +606,9 @@ OMR::Z::CodeGenerator::CodeGenerator()
       _callsForPreloadList = new (self()->trHeapMemory()) TR::list<TR_BranchPreloadCallData*>(getTypedAllocator<TR_BranchPreloadCallData*>(comp->allocator()));
       }
 
-   // Check if platform supports highword facility - both hardware and OS combination.
-   if (self()->getS390ProcessorInfo()->supportsArch(TR_S390ProcessorInfo::TR_z196) && !comp->getOption(TR_MimicInterpreterFrameShape))
+   if (TR::Compiler->target.cpu.getS390SupportsHPRDebug() && !comp->getOption(TR_DisableHighWordRA) && !comp->getOption(TR_MimicInterpreterFrameShape))
       {
-      // On 31-bit zlinux we need to check RAS support
-      if (!TR::Compiler->target.isLinux() || TR::Compiler->target.is64Bit() || TR::Compiler->target.cpu.getS390SupportsHPRDebug())
-         self()->setSupportsHighWordFacility(true);
+      self()->setSupportsHighWordFacility(true);
       }
 
    self()->setOnDemandLiteralPoolRun(true);
@@ -825,7 +822,6 @@ OMR::Z::CodeGenerator::getGlobalGPRFromHPR (TR_GlobalRegisterNumber n)
 
 bool OMR::Z::CodeGenerator::prepareForGRA()
    {
-   bool enableHighWordGRA = self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_DisableHighWordRA);
    bool enableVectorGRA = self()->getSupportsVectorRegisters() && !self()->comp()->getOption(TR_DisableVectorRegGRA);
 
    if (!_globalRegisterTable)
@@ -879,7 +875,7 @@ bool OMR::Z::CodeGenerator::prepareForGRA()
       // Initialize _globalGPRsPreservedAcrossCalls and _globalFPRsPreservedAcrossCalls
       // We call init here because getNumberOfGlobal[FG]PRs() is initialized during the call to initialize() above.
       //
-      if (enableHighWordGRA)
+      if (self()->supportsHighWordFacility())
          {
          _globalGPRsPreservedAcrossCalls.init(NUM_S390_GPR + NUM_S390_FPR + NUM_S390_HPR, self()->trMemory());
          _globalFPRsPreservedAcrossCalls.init(NUM_S390_GPR + NUM_S390_FPR + NUM_S390_HPR, self()->trMemory());
@@ -920,7 +916,7 @@ bool OMR::Z::CodeGenerator::prepareForGRA()
             TR_ASSERT(reg != -1, "Register pressure simulator doesn't support gaps in the global register table; reg %d must be removed", grn);
             if (self()->getFirstGlobalGPR() <= grn && grn <= self()->getLastGlobalGPR())
                {
-               if (enableHighWordGRA && self()->getFirstGlobalHPR() <= grn)
+               if (self()->supportsHighWordFacility() && self()->getFirstGlobalHPR() <= grn)
                   {
                   // this is a bit tricky, we consider Global HPRs part of Global GPRs
                   _globalRegisterBitVectors[ TR_hprSpill ].set(grn);
@@ -943,7 +939,7 @@ bool OMR::Z::CodeGenerator::prepareForGRA()
                _globalRegisterBitVectors[ TR_volatileSpill ].set(grn);
             if (linkage->getIntegerArgument(reg) || linkage->getFloatArgument(reg))
                {
-               if ((enableHighWordGRA) && (grn >= self()->getFirstGlobalGPR() && grn <= self()->getLastGlobalGPR()))
+               if ((self()->supportsHighWordFacility()) && (grn >= self()->getFirstGlobalGPR() && grn <= self()->getLastGlobalGPR()))
                   {
                   TR_GlobalRegisterNumber grnHPR = self()->getFirstGlobalHPR() - self()->getFirstGlobalGPR() + grn;
                   _globalRegisterBitVectors[ TR_linkageSpill  ].set(grnHPR);
@@ -2631,15 +2627,15 @@ OMR::Z::CodeGenerator::doRegisterAssignment(TR_RegisterKinds kindsToAssign)
 
       self()->tracePreRAInstruction(instructionCursor);
 
-      if (self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_DisableHighWordRA) && !self()->comp()->getOption(TR_DisableHPRUpgrade))
+      if (self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_DisableHPRUpgrade))
          {
          TR::Instruction * newInst = self()->upgradeToHPRInstruction(instructionCursor);
          if (newInst)
             {
             instructionCursor = newInst;
             }
          }
-      if (self()->supportsHighWordFacility() && self()->comp()->getOption(TR_DisableHighWordRA))
+      if (self()->supportsHighWordFacility())
          self()->setAvailableHPRSpillMask(0xffff0000);
 
       prevInstruction = instructionCursor->getPrev();
@@ -4997,7 +4993,7 @@ OMR::Z::CodeGenerator::buildRegisterMapForInstruction(TR_GCStackMap * map)
    TR::GCStackAtlas * atlas = self()->getStackAtlas();
 
 
-   if (self()->supportsHighWordFacility() && !self()->comp()->getOption(TR_DisableHighWordRA))
+   if (self()->supportsHighWordFacility())
       {
       for (int32_t i = TR::RealRegister::FirstHPR; i <= TR::RealRegister::LastHPR; i++)
          {

compiler/z/codegen/OMRInstruction.cpp

@@ -342,7 +342,6 @@ OMR::Z::Instruction::matchesAnyRegister(TR::Register * reg, TR::Register * instR
 
    bool enableHighWordRA =
       self()->cg()->supportsHighWordFacility() &&
-      !self()->cg()->comp()->getOption(TR_DisableHighWordRA) &&
       (reg->getKind()!=TR_FPR)                       &&
       (instReg->getKind()!=TR_FPR) &&
       (reg->getKind()!=TR_VRF) &&
@@ -764,7 +763,7 @@ OMR::Z::Instruction::assignRegisters(TR_RegisterKinds kindToBeAssigned)
                }
             }
 
-         if (self()->cg()->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA))
+         if (self()->cg()->supportsHighWordFacility())
             {
             for (int32_t i = TR::RealRegister::FirstHPR; i <= TR::RealRegister::LastHPR; i++)
                {
@@ -784,7 +783,7 @@ OMR::Z::Instruction::assignRegisters(TR_RegisterKinds kindToBeAssigned)
             machine->setVirtualAssociatedWithReal((TR::RealRegister::RegNum) (j + 1), virtReg);
             }
 
-         if(self()->cg()->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA))
+         if(self()->cg()->supportsHighWordFacility())
             {
             for (int32_t j = 0; j < TR::RealRegister::LastHPR-TR::RealRegister::FirstHPR; ++j)
                {
@@ -1012,7 +1011,7 @@ OMR::Z::Instruction::useSourceRegister(TR::Register * reg)
       }
 
    // mark used bit for HW/LW virtual regs
-   if (self()->cg()->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA))
+   if (self()->cg()->supportsHighWordFacility())
       {
       if (!self()->isHPRUpgradable(_targetRegSize+_sourceRegSize-1))
          {
@@ -1156,7 +1155,7 @@ OMR::Z::Instruction::useTargetRegister(TR::Register* reg)
          }
 
    // mark used bit for HW/LW virtual regs
-   if (self()->cg()->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA))
+   if (self()->cg()->supportsHighWordFacility())
       {
       if (!self()->isHPRUpgradable(_targetRegSize+_sourceRegSize-1))
          {
@@ -1527,15 +1526,15 @@ OMR::Z::Instruction::assignOrderedRegisters(TR_RegisterKinds kindToBeAssigned)
       if (!_targetReg[i]->getRegisterPair())
          continue;
 
-      if (self()->cg()->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA))
+      if (self()->cg()->supportsHighWordFacility())
          _targetReg[i]->setAssignToHPR(false);
       TR::Register *virtReg=_targetReg[i];
       _targetReg[i] = self()->assignRegisterNoDependencies(virtReg);
       _targetReg[i]->block();
 
       tgtAssigned[i] = 2;
 
-      if (self()->cg()->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA))
+      if (self()->cg()->supportsHighWordFacility())
          {
          // don't need to block HPR here beacuse no Highword instruction uses register pair
          // but make sure we do not spill to the targetReg's HPR (even if it became free) while assigning sourceReg
@@ -1555,7 +1554,7 @@ OMR::Z::Instruction::assignOrderedRegisters(TR_RegisterKinds kindToBeAssigned)
       if (!_sourceReg[i]->getRegisterPair())
          continue;
 
-      if (self()->cg()->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA))
+      if (self()->cg()->supportsHighWordFacility())
          (_sourceReg[i])->setAssignToHPR(false);
       (_sourceReg[i]) = self()->assignRegisterNoDependencies(_sourceReg[i]);
       (_sourceReg[i])->block();
@@ -1575,7 +1574,7 @@ OMR::Z::Instruction::assignOrderedRegisters(TR_RegisterKinds kindToBeAssigned)
 
          registerOperandNum = (_targetReg < _sourceReg) ? i+1 : _sourceRegSize+i+1;
 
-         if (self()->cg()->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA))
+         if (self()->cg()->supportsHighWordFacility())
             {
             if ((self()->getOpCodeValue() == TR::InstOpCode::RISBLG || self()->getOpCodeValue() == TR::InstOpCode::RISBHG) &&
                 ((TR::S390RIEInstruction *)self())->getExtendedHighWordOpCode().getOpCodeValue() != TR::InstOpCode::BAD)
@@ -1598,7 +1597,7 @@ OMR::Z::Instruction::assignOrderedRegisters(TR_RegisterKinds kindToBeAssigned)
             }
          _targetReg[i] = self()->assignRegisterNoDependencies(_targetReg[i]);
 
-         if (self()->cg()->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA) &&
+         if (self()->cg()->supportsHighWordFacility() &&
              _targetReg[i]->getKind() != TR_FPR && _targetReg[i]->getKind() != TR_VRF)
             {
             if (toRealRegister(_targetReg[i])->getState() == TR::RealRegister::Free && targetRegIs64Bit)
@@ -1669,7 +1668,7 @@ OMR::Z::Instruction::assignOrderedRegisters(TR_RegisterKinds kindToBeAssigned)
    if (_sourceReg)
       {
       registerOperandNum = (_targetReg < _sourceReg) ? _targetRegSize+1 : 1;
-      if (self()->cg()->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA))
+      if (self()->cg()->supportsHighWordFacility())
          {
          if (firstNonPairSourceRegister)
             {
@@ -1705,7 +1704,7 @@ OMR::Z::Instruction::assignOrderedRegisters(TR_RegisterKinds kindToBeAssigned)
       {
       for (i = 0; i < _sourceMemSize; ++i)
          {
-         if (self()->cg()->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA))
+         if (self()->cg()->supportsHighWordFacility())
             {
             if (_sourceMem[i]->getBaseRegister())
                {
@@ -1724,7 +1723,7 @@ OMR::Z::Instruction::assignOrderedRegisters(TR_RegisterKinds kindToBeAssigned)
       {
       for (i = 0; i < _targetMemSize; ++i)
          {
-         if (self()->cg()->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA))
+         if (self()->cg()->supportsHighWordFacility())
             {
             if (_targetMem[i]->getBaseRegister())
                {
@@ -2334,7 +2333,7 @@ OMR::Z::Instruction::setUseDefRegisters(bool updateDependencies)
       }
 
    // set all HPRs to alias GPRs
-   if (self()->cg()->supportsHighWordFacility() && !comp->getOption(TR_DisableHighWordRA))
+   if (self()->cg()->supportsHighWordFacility())
       {
       if (_useRegs)
          {

compiler/z/codegen/OMRLinkage.cpp

@@ -395,8 +395,6 @@ OMR::Z::Linkage::saveArguments(void * cursor, bool genBinary, bool InPreProlog,
    int8_t gprSize = self()->cg()->machine()->getGPRSize();
 
    bool unconditionalSave  = false;
-   bool enableHighWordRA = self()->cg()->supportsHighWordFacility() && !self()->comp()->getOption(TR_DisableHighWordRA);
-
 
    // If we use preexistence or FSD or HCR, then we could be reverting back to the
    // interpreter by creating prePrologue snippets.  In such cases, we need
@@ -414,7 +412,7 @@ OMR::Z::Linkage::saveArguments(void * cursor, bool genBinary, bool InPreProlog,
    //  -> set means free
    // Keep a list of global registers
    //
-   if (enableHighWordRA)
+   if (self()->cg()->supportsHighWordFacility())
       {
       freeScratchable.init(TR::RealRegister::LastHPR + 1, self()->trMemory());
       globalAllocatedRegisters.init(TR::RealRegister::LastHPR + 1, self()->trMemory());
@@ -577,7 +575,7 @@ OMR::Z::Linkage::saveArguments(void * cursor, bool genBinary, bool InPreProlog,
          }
 
       if (ai >= 0 &&
-         loadOpCode == TR::InstOpCode::L && enableHighWordRA && self()->getRealRegister(REGNUM(ai))->isHighWordRegister())
+         loadOpCode == TR::InstOpCode::L && self()->cg()->supportsHighWordFacility() && self()->getRealRegister(REGNUM(ai))->isHighWordRegister())
          loadOpCode = TR::InstOpCode::LFH;
 
       if (((self()->isSmallIntParmsAlignedRight() && paramCursor->getType().isIntegral()) ||
@@ -925,7 +923,7 @@ OMR::Z::Linkage::saveArguments(void * cursor, bool genBinary, bool InPreProlog,
                         }
                      else
                         {
-                        if (enableHighWordRA && self()->getRealRegister(REGNUM(ai))->isHighWordRegister())
+                        if (self()->cg()->supportsHighWordFacility() && self()->getRealRegister(REGNUM(ai))->isHighWordRegister())
                            {
                            cursor = generateExtendedHighWordInstruction(firstNode, self()->cg(), TR::InstOpCode::LHLR, self()->getRealRegister(REGNUM(ai)),
                                                           self()->getRealRegister(regNum), 0, (TR::Instruction *) cursor);
@@ -1217,7 +1215,7 @@ OMR::Z::Linkage::saveArguments(void * cursor, bool genBinary, bool InPreProlog,
             switch(busyMoves[2][i1])
                {
                case 0: // Reg 2 Reg
-                  if (enableHighWordRA && self()->getRealRegister(REGNUM(target))->isHighWordRegister())
+                  if (self()->cg()->supportsHighWordFacility() && self()->getRealRegister(REGNUM(target))->isHighWordRegister())
                      {
                      cursor = generateExtendedHighWordInstruction(firstNode, self()->cg(), TR::InstOpCode::LHLR, self()->getRealRegister(REGNUM(target)),
                                                                   self()->getRealRegister(REGNUM(source)), 0, (TR::Instruction *) cursor);