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Improve readability of X86 CPU model and processor macros
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Add underscores for improved readability.

Signed-off-by: Daryl Maier <maier@ca.ibm.com>
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@0xdaryl
0xdaryl committed May 28, 2024
1 parent 01374a4 commit 9d8a6a4
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Showing 5 changed files with 172 additions and 147 deletions.
24 changes: 12 additions & 12 deletions compiler/x/codegen/IntegerMultiplyDecomposer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -98,21 +98,21 @@ TR::Register *TR_X86IntegerMultiplyDecomposer::decomposeIntegerMultiplier(int32_
const integerMultiplyComposition& composition = _integerMultiplySolutions[decompositionIndex];
if (composition._subsequentShiftTooExpensive == false)
{
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTELCORE2) == cg()->getX86ProcessorInfo().isIntelCore2(), "isIntelCore2 failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTELNEHALEM) == cg()->getX86ProcessorInfo().isIntelNehalem(), "isIntelNehalem failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTELWESTMERE) == cg()->getX86ProcessorInfo().isIntelWestmere(), "isIntelWestmere failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTELSANDYBRIDGE) == cg()->getX86ProcessorInfo().isIntelSandyBridge(), "isIntelSandyBridge failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_AMDFAMILY15H) == cg()->getX86ProcessorInfo().isAMD15h(), "isAMD15h failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_AMDOPTERON) == cg()->getX86ProcessorInfo().isAMDOpteron(), "isAMDOpteron failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_CORE2) == cg()->getX86ProcessorInfo().isIntelCore2(), "isIntelCore2 failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_NEHALEM) == cg()->getX86ProcessorInfo().isIntelNehalem(), "isIntelNehalem failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_WESTMERE) == cg()->getX86ProcessorInfo().isIntelWestmere(), "isIntelWestmere failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_SANDYBRIDGE) == cg()->getX86ProcessorInfo().isIntelSandyBridge(), "isIntelSandyBridge failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_AMD_FAMILY15H) == cg()->getX86ProcessorInfo().isAMD15h(), "isAMD15h failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_AMD_OPTERON) == cg()->getX86ProcessorInfo().isAMDOpteron(), "isAMDOpteron failed\n");

target = generateDecompositionInstructions(decompositionIndex, tempRegArraySize, tempRegArray);
if (shiftAmount < 3 &&
!comp->target().cpu.is(OMR_PROCESSOR_X86_INTELCORE2) &&
!comp->target().cpu.is(OMR_PROCESSOR_X86_INTELNEHALEM) &&
!comp->target().cpu.is(OMR_PROCESSOR_X86_INTELWESTMERE) &&
!comp->target().cpu.is(OMR_PROCESSOR_X86_INTELSANDYBRIDGE) &&
!comp->target().cpu.is(OMR_PROCESSOR_X86_AMDFAMILY15H) &&
!comp->target().cpu.is(OMR_PROCESSOR_X86_AMDOPTERON)) // TODO:: P3 should go straight to else and use shift always
!comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_CORE2) &&
!comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_NEHALEM) &&
!comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_WESTMERE) &&
!comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_SANDYBRIDGE) &&
!comp->target().cpu.is(OMR_PROCESSOR_X86_AMD_FAMILY15H) &&
!comp->target().cpu.is(OMR_PROCESSOR_X86_AMD_OPTERON)) // TODO:: P3 should go straight to else and use shift always
{
for (; shiftAmount > 0; --shiftAmount)
{
Expand Down
14 changes: 7 additions & 7 deletions compiler/x/codegen/OMRCodeGenerator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -270,8 +270,8 @@ OMR::X86::CodeGenerator::initializeX86(TR::Compilation *comp)
*
* TODO: Need to figure out from which mode of Broadwell start supporting TM
*/
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTELHASWELL) == getX86ProcessorInfo().isIntelHaswell(), "isIntelHaswell() failed\n");
if (!comp->target().cpu.is(OMR_PROCESSOR_X86_INTELHASWELL))
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_HASWELL) == getX86ProcessorInfo().isIntelHaswell(), "isIntelHaswell() failed\n");
if (!comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_HASWELL))
{
if (comp->target().is64Bit())
{
Expand Down Expand Up @@ -303,9 +303,9 @@ OMR::X86::CodeGenerator::initializeX86(TR::Compilation *comp)
// Enable software prefetch of the TLH and configure the TLH prefetching
// geometry.
//
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTELCORE2) == comp->cg()->getX86ProcessorInfo().isIntelCore2(), "isIntelCore2() failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTELNEHALEM) == comp->cg()->getX86ProcessorInfo().isIntelNehalem(), "isIntelNehalem() failed\n");
if (((!comp->getOption(TR_DisableTLHPrefetch) && (comp->target().cpu.is(OMR_PROCESSOR_X86_INTELCORE2) || comp->target().cpu.is(OMR_PROCESSOR_X86_INTELNEHALEM))) ||
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_CORE2) == comp->cg()->getX86ProcessorInfo().isIntelCore2(), "isIntelCore2() failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_NEHALEM) == comp->cg()->getX86ProcessorInfo().isIntelNehalem(), "isIntelNehalem() failed\n");
if (((!comp->getOption(TR_DisableTLHPrefetch) && (comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_CORE2) || comp->target().cpu.is(OMR_PROCESSOR_X86_INTEL_NEHALEM))) ||
(comp->getOption(TR_TLHPrefetch) && self()->targetSupportsSoftwarePrefetches())))
{
self()->setEnableTLHPrefetching();
Expand Down Expand Up @@ -459,9 +459,9 @@ OMR::X86::CodeGenerator::initializeX86(TR::Compilation *comp)
//
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.isGenuineIntel() == getX86ProcessorInfo().isGenuineIntel(), "isGenuineIntel() failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.isAuthenticAMD() == getX86ProcessorInfo().isAuthenticAMD(), "isAuthenticAMD() failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_AMDFAMILY15H) == getX86ProcessorInfo().isAMD15h(), "isAMD15h() failed\n");
TR_ASSERT_FATAL(comp->compileRelocatableCode() || comp->isOutOfProcessCompilation() || comp->compilePortableCode() || comp->target().cpu.is(OMR_PROCESSOR_X86_AMD_FAMILY15H) == getX86ProcessorInfo().isAMD15h(), "isAMD15h() failed\n");
int32_t boundary;
if (comp->target().cpu.isGenuineIntel() || (comp->target().cpu.isAuthenticAMD() && comp->target().cpu.is(OMR_PROCESSOR_X86_AMDFAMILY15H)))
if (comp->target().cpu.isGenuineIntel() || (comp->target().cpu.isAuthenticAMD() && comp->target().cpu.is(OMR_PROCESSOR_X86_AMD_FAMILY15H)))
boundary = 32;
else
{
Expand Down
96 changes: 48 additions & 48 deletions compiler/x/env/OMRCPU.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -221,7 +221,7 @@ OMR::X86::CPU::prefersMultiByteNOP()
if (TR::Compiler->omrPortLib == NULL)
return TR::CodeGenerator::getX86ProcessorInfo().prefersMultiByteNOP();

return self()->isGenuineIntel() && !self()->is(OMR_PROCESSOR_X86_INTELPENTIUM);
return self()->isGenuineIntel() && !self()->is(OMR_PROCESSOR_X86_INTEL_PENTIUM);
}

bool
Expand Down Expand Up @@ -265,35 +265,35 @@ OMR::X86::CPU::is_test(OMRProcessorArchitecture p)
{
switch(p)
{
case OMR_PROCESSOR_X86_INTELWESTMERE:
case OMR_PROCESSOR_X86_INTEL_WESTMERE:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelWestmere() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTELNEHALEM:
case OMR_PROCESSOR_X86_INTEL_NEHALEM:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelNehalem() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTELPENTIUM:
case OMR_PROCESSOR_X86_INTEL_PENTIUM:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelPentium() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTELP6:
case OMR_PROCESSOR_X86_INTEL_P6:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelP6() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTELPENTIUM4:
case OMR_PROCESSOR_X86_INTEL_PENTIUM4:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelPentium4() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTELCORE2:
case OMR_PROCESSOR_X86_INTEL_CORE2:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelCore2() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTELTULSA:
case OMR_PROCESSOR_X86_INTEL_TULSA:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelTulsa() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTELSANDYBRIDGE:
case OMR_PROCESSOR_X86_INTEL_SANDYBRIDGE:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelSandyBridge() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTELIVYBRIDGE:
case OMR_PROCESSOR_X86_INTEL_IVYBRIDGE:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelIvyBridge() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTELHASWELL:
case OMR_PROCESSOR_X86_INTEL_HASWELL:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelHaswell() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTELBROADWELL:
case OMR_PROCESSOR_X86_INTEL_BROADWELL:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelBroadwell() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_INTELSKYLAKE:
case OMR_PROCESSOR_X86_INTEL_SKYLAKE:
return TR::CodeGenerator::getX86ProcessorInfo().isIntelSkylake() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_AMDATHLONDURON:
case OMR_PROCESSOR_X86_AMD_ATHLONDURON:
return TR::CodeGenerator::getX86ProcessorInfo().isAMDAthlonDuron() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_AMDOPTERON:
case OMR_PROCESSOR_X86_AMD_OPTERON:
return TR::CodeGenerator::getX86ProcessorInfo().isAMDOpteron() == (_processorDescription.processor == p);
case OMR_PROCESSOR_X86_AMDFAMILY15H:
case OMR_PROCESSOR_X86_AMD_FAMILY15H:
return TR::CodeGenerator::getX86ProcessorInfo().isAMD15h() == (_processorDescription.processor == p);
default:
return false;
Expand Down Expand Up @@ -419,49 +419,49 @@ OMR::X86::CPU::is_old_api(OMRProcessorArchitecture p)
bool ans = false;
switch(p)
{
case OMR_PROCESSOR_X86_INTELWESTMERE:
case OMR_PROCESSOR_X86_INTEL_WESTMERE:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelWestmere();
break;
case OMR_PROCESSOR_X86_INTELNEHALEM:
case OMR_PROCESSOR_X86_INTEL_NEHALEM:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelNehalem();
break;
case OMR_PROCESSOR_X86_INTELPENTIUM:
case OMR_PROCESSOR_X86_INTEL_PENTIUM:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelPentium();
break;
case OMR_PROCESSOR_X86_INTELP6:
case OMR_PROCESSOR_X86_INTEL_P6:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelP6();
break;
case OMR_PROCESSOR_X86_INTELPENTIUM4:
case OMR_PROCESSOR_X86_INTEL_PENTIUM4:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelPentium4();
break;
case OMR_PROCESSOR_X86_INTELCORE2:
case OMR_PROCESSOR_X86_INTEL_CORE2:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelCore2();
break;
case OMR_PROCESSOR_X86_INTELTULSA:
case OMR_PROCESSOR_X86_INTEL_TULSA:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelTulsa();
break;
case OMR_PROCESSOR_X86_INTELSANDYBRIDGE:
case OMR_PROCESSOR_X86_INTEL_SANDYBRIDGE:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelSandyBridge();
break;
case OMR_PROCESSOR_X86_INTELIVYBRIDGE:
case OMR_PROCESSOR_X86_INTEL_IVYBRIDGE:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelIvyBridge();
break;
case OMR_PROCESSOR_X86_INTELHASWELL:
case OMR_PROCESSOR_X86_INTEL_HASWELL:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelHaswell();
break;
case OMR_PROCESSOR_X86_INTELBROADWELL:
case OMR_PROCESSOR_X86_INTEL_BROADWELL:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelBroadwell();
break;
case OMR_PROCESSOR_X86_INTELSKYLAKE:
case OMR_PROCESSOR_X86_INTEL_SKYLAKE:
ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelSkylake();
break;
case OMR_PROCESSOR_X86_AMDATHLONDURON:
case OMR_PROCESSOR_X86_AMD_ATHLONDURON:
ans = TR::CodeGenerator::getX86ProcessorInfo().isAMDAthlonDuron();
break;
case OMR_PROCESSOR_X86_AMDOPTERON:
case OMR_PROCESSOR_X86_AMD_OPTERON:
ans = TR::CodeGenerator::getX86ProcessorInfo().isAMDOpteron();
break;
case OMR_PROCESSOR_X86_AMDFAMILY15H:
case OMR_PROCESSOR_X86_AMD_FAMILY15H:
ans = TR::CodeGenerator::getX86ProcessorInfo().isAMD15h();
break;
default:
Expand Down Expand Up @@ -637,71 +637,71 @@ OMR::X86::CPU::getProcessorName()
const char* returnString = "";
switch(_processorDescription.processor)
{
case OMR_PROCESSOR_X86_INTELPENTIUM:
case OMR_PROCESSOR_X86_INTEL_PENTIUM:
returnString = "X86 Intel Pentium";
break;

case OMR_PROCESSOR_X86_INTELP6:
case OMR_PROCESSOR_X86_INTEL_P6:
returnString = "X86 Intel P6";
break;

case OMR_PROCESSOR_X86_INTELPENTIUM4:
case OMR_PROCESSOR_X86_INTEL_PENTIUM4:
returnString = "X86 Intel Netburst Microarchitecture";
break;

case OMR_PROCESSOR_X86_INTELCORE2:
case OMR_PROCESSOR_X86_INTEL_CORE2:
returnString = "X86 Intel Core2 Microarchitecture";
break;

case OMR_PROCESSOR_X86_INTELTULSA:
case OMR_PROCESSOR_X86_INTEL_TULSA:
returnString = "X86 Intel Tulsa";
break;

case OMR_PROCESSOR_X86_INTELNEHALEM:
case OMR_PROCESSOR_X86_INTEL_NEHALEM:
returnString = "X86 Intel Nehalem";
break;

case OMR_PROCESSOR_X86_INTELWESTMERE:
case OMR_PROCESSOR_X86_INTEL_WESTMERE:
returnString = "X86 Intel Westmere";
break;

case OMR_PROCESSOR_X86_INTELSANDYBRIDGE:
case OMR_PROCESSOR_X86_INTEL_SANDYBRIDGE:
returnString = "X86 Intel Sandy Bridge";
break;

case OMR_PROCESSOR_X86_INTELIVYBRIDGE:
case OMR_PROCESSOR_X86_INTEL_IVYBRIDGE:
returnString = "X86 Intel Ivy Bridge";
break;

case OMR_PROCESSOR_X86_INTELHASWELL:
case OMR_PROCESSOR_X86_INTEL_HASWELL:
returnString = "X86 Intel Haswell";
break;

case OMR_PROCESSOR_X86_INTELBROADWELL:
case OMR_PROCESSOR_X86_INTEL_BROADWELL:
returnString = "X86 Intel Broadwell";
break;

case OMR_PROCESSOR_X86_INTELSKYLAKE:
case OMR_PROCESSOR_X86_INTEL_SKYLAKE:
returnString = "X86 Intel Skylake";
break;

case OMR_PROCESSOR_X86_AMDK5:
case OMR_PROCESSOR_X86_AMD_K5:
returnString = "X86 AMDK5";
break;

case OMR_PROCESSOR_X86_AMDK6:
case OMR_PROCESSOR_X86_AMD_K6:
returnString = "X86 AMDK6";
break;

case OMR_PROCESSOR_X86_AMDATHLONDURON:
case OMR_PROCESSOR_X86_AMD_ATHLONDURON:
returnString = "X86 AMD Athlon-Duron";
break;

case OMR_PROCESSOR_X86_AMDOPTERON:
case OMR_PROCESSOR_X86_AMD_OPTERON:
returnString = "X86 AMD Opteron";
break;

case OMR_PROCESSOR_X86_AMDFAMILY15H:
case OMR_PROCESSOR_X86_AMD_FAMILY15H:
returnString = "X86 AMD Family 15h";
break;

Expand Down
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