Convert RegisterDependencyGroup to an extensible class on AArch64

Repeat the exercise from Z on AArch64.
eclipse · May 11, 2021 · b45d152 · b45d152
1 parent 02edfb9
commit b45d152
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Showing 4 changed files with 124 additions and 239 deletions.
diff --git a/compiler/aarch64/codegen/ARM64Debug.cpp b/compiler/aarch64/codegen/ARM64Debug.cpp
@@ -1616,7 +1616,7 @@ TR_Debug::print(TR::FILE *pOutFile, TR::RegisterDependencyConditions *conditions
 void
 TR_Debug::printAssocRegDirective(TR::FILE *pOutFile, TR::Instruction *instr)
    {
-   TR_ARM64RegisterDependencyGroup * depGroup = instr->getDependencyConditions()->getPostConditions();
+   TR::RegisterDependencyGroup * depGroup = instr->getDependencyConditions()->getPostConditions();
 
    printPrefix(pOutFile, instr);
    trfprintf(pOutFile, "%s", getOpCodeName(&instr->getOpCode()));

diff --git a/compiler/aarch64/codegen/OMRRegisterDependency.cpp b/compiler/aarch64/codegen/OMRRegisterDependency.cpp
@@ -34,6 +34,15 @@
 // Replace this by #include "codegen/Instruction.hpp" when available for aarch64
 namespace TR { class Instruction; }
 
+OMR::ARM64::RegisterDependencyConditions::RegisterDependencyConditions(uint16_t numPreConds, uint16_t numPostConds, TR_Memory * m)
+   : _preConditions(new (numPreConds, m) TR::RegisterDependencyGroup),
+      _postConditions(new (numPostConds, m) TR::RegisterDependencyGroup),
+      _numPreConditions(numPreConds),
+      _addCursorForPre(0),
+      _numPostConditions(numPostConds),
+      _addCursorForPost(0)
+   {}
+
 OMR::ARM64::RegisterDependencyConditions::RegisterDependencyConditions(
                                        TR::CodeGenerator *cg,
                                        TR::Node          *node,
@@ -47,8 +56,8 @@ OMR::ARM64::RegisterDependencyConditions::RegisterDependencyConditions(
 
    cg->comp()->incVisitCount();
 
-   _preConditions = new (totalNum, cg->trMemory()) TR_ARM64RegisterDependencyGroup;
-   _postConditions = new (totalNum, cg->trMemory()) TR_ARM64RegisterDependencyGroup;
+   _preConditions = new (totalNum, cg->trMemory()) TR::RegisterDependencyGroup;
+   _postConditions = new (totalNum, cg->trMemory()) TR::RegisterDependencyGroup;
    _numPreConditions = totalNum;
    _addCursorForPre = 0;
    _numPostConditions = totalNum;
@@ -141,6 +150,74 @@ void OMR::ARM64::RegisterDependencyConditions::unionNoRegPostCondition(TR::Regis
    addPostCondition(reg, TR::RealRegister::NoReg);
    }
 
+void OMR::ARM64::RegisterDependencyConditions::addPreCondition(TR::Register *vr, TR::RealRegister::RegNum rr, uint8_t flag)
+   {
+   TR_ASSERT(_addCursorForPre < _numPreConditions, " Pre Condition array bounds overflow");
+   _preConditions->setDependencyInfo(_addCursorForPre++, vr, rr, flag);
+   }
+
+void OMR::ARM64::RegisterDependencyConditions::addPostCondition(TR::Register *vr, TR::RealRegister::RegNum rr, uint8_t flag)
+   {
+   TR_ASSERT(_addCursorForPost < _numPostConditions, " Post Condition array bounds overflow");
+   _postConditions->setDependencyInfo(_addCursorForPost++, vr, rr, flag);
+   }
+
+void OMR::ARM64::RegisterDependencyConditions::assignPreConditionRegisters(TR::Instruction *currentInstruction, TR_RegisterKinds kindToBeAssigned, TR::CodeGenerator *cg)
+   {
+   if (_preConditions != NULL)
+      {
+      cg->clearRegisterAssignmentFlags();
+      cg->setRegisterAssignmentFlag(TR_PreDependencyCoercion);
+      _preConditions->assignRegisters(currentInstruction, kindToBeAssigned, _addCursorForPre, cg);
+      }
+   }
+
+void OMR::ARM64::RegisterDependencyConditions::assignPostConditionRegisters(TR::Instruction *currentInstruction, TR_RegisterKinds kindToBeAssigned, TR::CodeGenerator *cg)
+   {
+   if (_postConditions != NULL)
+      {
+      cg->clearRegisterAssignmentFlags();
+      cg->setRegisterAssignmentFlag(TR_PostDependencyCoercion);
+      _postConditions->assignRegisters(currentInstruction, kindToBeAssigned, _addCursorForPost, cg);
+      }
+   }
+
+TR::Register *OMR::ARM64::RegisterDependencyConditions::searchPreConditionRegister(TR::RealRegister::RegNum rr)
+   {
+   return(_preConditions==NULL?NULL:_preConditions->searchForRegister(rr, _addCursorForPre));
+   }
+
+TR::Register *OMR::ARM64::RegisterDependencyConditions::searchPostConditionRegister(TR::RealRegister::RegNum rr)
+   {
+   return(_postConditions==NULL?NULL:_postConditions->searchForRegister(rr, _addCursorForPost));
+   }
+
+uint32_t OMR::ARM64::RegisterDependencyConditions::setNumPreConditions(uint16_t n, TR_Memory * m)
+   {
+   if (_preConditions == NULL)
+      {
+      _preConditions = new (n, m) TR::RegisterDependencyGroup;
+      }
+   if (_addCursorForPre > n)
+      {
+      _addCursorForPre = n;
+      }
+   return (_numPreConditions = n);
+   }
+
+uint32_t OMR::ARM64::RegisterDependencyConditions::setNumPostConditions(uint16_t n, TR_Memory * m)
+   {
+   if (_postConditions == NULL)
+      {
+      _postConditions = new (n, m) TR::RegisterDependencyGroup;
+      }
+   if (_addCursorForPost > n)
+      {
+      _addCursorForPost = n;
+      }
+   return (_numPostConditions = n);
+   }
+
 bool OMR::ARM64::RegisterDependencyConditions::refsRegister(TR::Register *r)
    {
    for (uint16_t i = 0; i < _addCursorForPre; i++)
@@ -329,12 +406,12 @@ OMR::ARM64::RegisterDependencyConditions::clone(
 void OMR::ARM64::RegisterDependencyConditions::stopUsingDepRegs(TR::CodeGenerator *cg, TR::Register *returnRegister)
    {
    if (_preConditions != NULL)
-      _preConditions->stopUsingDepRegs(getAddCursorForPre(), returnRegister, cg);
+      _preConditions->stopUsingDepRegs(getAddCursorForPre(), NULL, returnRegister, cg);
    if (_postConditions != NULL)
-      _postConditions->stopUsingDepRegs(getAddCursorForPost(), returnRegister, cg);
+      _postConditions->stopUsingDepRegs(getAddCursorForPost(), NULL, returnRegister, cg);
    }
 
-void TR_ARM64RegisterDependencyGroup::assignRegisters(
+void OMR::ARM64::RegisterDependencyGroup::assignRegisters(
                         TR::Instruction *currentInstruction,
                         TR_RegisterKinds kindToBeAssigned,
                         uint32_t numberOfRegisters,
@@ -536,3 +613,12 @@ void TR_ARM64RegisterDependencyGroup::assignRegisters(
          }
       }
    }
+
+void
+OMR::Z::RegisterDependencyConditions::stopUsingDepRegs(TR::CodeGenerator *cg, TR::Register *ret1, TR::Register *ret2)
+   {
+   if (_preConditions != NULL)
+      _preConditions->stopUsingDepRegs(_addCursorForPre, ret1, ret2, cg);
+   if (_postConditions != NULL)
+      _postConditions->stopUsingDepRegs(_addCursorForPost, ret1, ret2, cg);
+   }