Replace instantiations of TR_X86OpCode with TR::InstOpCode

Now that we have multiple inheritence properly working, we can replace
all uses of `TR_X86OpCode` with `TR::InstOpCode`.

compiler/ras/Debug.hpp

@@ -113,7 +113,6 @@ struct J9AnnotationInfo;
 struct J9AnnotationInfoEntry;
 struct J9PortLibrary;
 
-class TR_X86OpCode;
 namespace TR { class X86LabelInstruction;                  }
 namespace TR { class X86PaddingInstruction;                }
 namespace TR { class X86AlignmentInstruction;              }
@@ -609,8 +608,8 @@ class TR_Debug
    virtual const char * getPerCodeCacheHelperName(TR_CCPreLoadedCode helper);
 
 #if defined(TR_TARGET_X86)
-   virtual const char * getOpCodeName(TR_X86OpCode *);
-   virtual const char * getMnemonicName(TR_X86OpCode *);
+   virtual const char * getOpCodeName(TR::InstOpCode *);
+   virtual const char * getMnemonicName(TR::InstOpCode *);
    virtual void         printReferencedRegisterInfo(TR::FILE *, TR::Instruction *);
    virtual void         dumpInstructionWithVFPState(TR::Instruction *instr, const TR_VFPState *prevState);
 

compiler/x/codegen/BinaryCommutativeAnalyser.cpp

@@ -172,11 +172,11 @@ TR::Register* TR_X86BinaryCommutativeAnalyser::genericAnalyserImpl(TR::Node
    else if (getCopyReg1())
       {
       TR::Register *tempReg;
-      if (TR_X86OpCode::fprOp(copyOpCode) == 0)
+      if (TR::InstOpCode::fprOp(copyOpCode) == 0)
          {
          tempReg = _cg->allocateRegister();
          }
-      else if (TR_X86OpCode::singleFPOp(copyOpCode))
+      else if (TR::InstOpCode::singleFPOp(copyOpCode))
          {
          tempReg = _cg->allocateSinglePrecisionRegister(TR_X87);
          }
@@ -191,11 +191,11 @@ TR::Register* TR_X86BinaryCommutativeAnalyser::genericAnalyserImpl(TR::Node
    else if (getCopyReg2())
       {
       TR::Register *tempReg;
-      if (TR_X86OpCode::fprOp(copyOpCode) == 0)
+      if (TR::InstOpCode::fprOp(copyOpCode) == 0)
          {
          tempReg = _cg->allocateRegister();
          }
-      else if (TR_X86OpCode::singleFPOp(copyOpCode))
+      else if (TR::InstOpCode::singleFPOp(copyOpCode))
          {
          tempReg = _cg->allocateSinglePrecisionRegister(TR_X87);
          }
@@ -887,7 +887,7 @@ TR::Register *TR_X86BinaryCommutativeAnalyser::integerAddAnalyserImpl(TR::Node
          }
 
       targetRegister = tempReg;
-      bool is64Bit = TR_X86OpCode(regRegOpCode).hasLongSource();
+      bool is64Bit = TR::InstOpCode(regRegOpCode).hasLongSource();
 
       // if eflags are required then we cannot use LEA as it doesn't set or use them
       if (needsEflags || (carry != 0))

compiler/x/codegen/DivideCheckSnippet.cpp

@@ -45,7 +45,7 @@ uint8_t *TR::X86DivideCheckSnippet::emitSnippetBody()
    // CMP realDivisorReg, -1
    //
    uint8_t rexPrefix = cg()->comp()->target().is64Bit() ? realDivisorReg->rexBits(TR::RealRegister::REX_B, false) : 0;
-   buffer = TR_X86OpCode(CMPRegImms(_divOp.isLong())).binary(buffer, rexPrefix);
+   buffer = TR::InstOpCode(CMPRegImms(_divOp.isLong())).binary(buffer, rexPrefix);
    realDivisorReg->setRMRegisterFieldInModRM(buffer-1);
    *buffer++ = -1;
 

compiler/x/codegen/FPTreeEvaluator.cpp

@@ -2151,8 +2151,8 @@ TR::Register *OMR::X86::TreeEvaluator::compareFloatOrDoubleForOrder(TR::Node
                                                                 TR::CodeGenerator *cg)
    {
    if (
-      ((TR_X86OpCode::singleFPOp(fpCmpRegRegOpCode) && cg->useSSEForSinglePrecision()) ||
-       (TR_X86OpCode::doubleFPOp(fpCmpRegRegOpCode) && cg->useSSEForDoublePrecision())))
+      ((TR::InstOpCode::singleFPOp(fpCmpRegRegOpCode) && cg->useSSEForSinglePrecision()) ||
+       (TR::InstOpCode::doubleFPOp(fpCmpRegRegOpCode) && cg->useSSEForDoublePrecision())))
       {
       TR_IA32XMMCompareAnalyser temp(cg);
       return temp.xmmCompareAnalyser(node, xmmCmpRegRegOpCode, xmmCmpRegMemOpCode);

compiler/x/codegen/OMRCodeGenerator.cpp

@@ -2723,14 +2723,14 @@ uint8_t *OMR::X86::CodeGenerator::generatePadding(uint8_t              *cursor,
          if (length >= 5)
             {
             length -= 5;
-            cursor = TR_X86OpCode(JMP4).binary(cursor);
+            cursor = TR::InstOpCode(JMP4).binary(cursor);
             *(int32_t*)cursor = length;
             cursor += 4;
             }
          else
             {
             length -= 2;
-            cursor = TR_X86OpCode(JMP1).binary(cursor);
+            cursor = TR::InstOpCode(JMP1).binary(cursor);
             *(int8_t*)cursor = length;
             cursor += 1;
             }

compiler/x/codegen/OMRInstruction.hpp

@@ -93,7 +93,7 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
    virtual char *description() { return "X86"; }
    virtual Kind getKind() { return IsNotExtended; }
 
-   TR_X86OpCode& getOpCode() { return _opcode; }
+   TR::InstOpCode& getOpCode() { return _opcode; }
    TR_X86OpCodes getOpCodeValue() { return _opcode.getOpCodeValue(); }
    TR_X86OpCodes setOpCodeValue(TR_X86OpCodes op) { return _opcode.setOpCodeValue(op); }
 
@@ -172,7 +172,7 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
 
    private:
 
-   TR_X86OpCode _opcode;
+   TR::InstOpCode _opcode;
    TR::RegisterDependencyConditions *_conditions;
    void assumeValidInstruction();
 

compiler/x/codegen/OMRTreeEvaluator.cpp

@@ -234,7 +234,7 @@ TR::Instruction *OMR::X86::TreeEvaluator::insertLoadConstant(TR::Node
       //
       if ((value == 0 || value == -1))
          {
-         uint8_t EFlags = TR_X86OpCode::getModifiedEFlags(ops[opsRow][((value == 0) ? XOR : OR)]);
+         uint8_t EFlags = TR::InstOpCode::getModifiedEFlags(ops[opsRow][((value == 0) ? XOR : OR)]);
 
          if (existsNextInstructionToTestFlags(currentInstruction, EFlags) || cg->requiresCarry())
             {
@@ -2927,7 +2927,7 @@ static TR::Register * inlineSinglePrecisionSQRT(TR::Node *node, TR::CodeGenerato
  */
 static TR::Register* inlineAtomicMemoryUpdate(TR::Node* node, TR_X86OpCodes op, TR::CodeGenerator* cg)
    {
-   TR_ASSERT((!TR_X86OpCode(op).hasLongSource() && !TR_X86OpCode(op).hasLongTarget()) || cg->comp()->target().is64Bit(), "64-bit instruction not supported on IA32");
+   TR_ASSERT((!TR::InstOpCode(op).hasLongSource() && !TR::InstOpCode(op).hasLongTarget()) || cg->comp()->target().is64Bit(), "64-bit instruction not supported on IA32");
    TR::Register* address = cg->evaluate(node->getChild(0));
    TR::Register* value   = cg->gprClobberEvaluate(node->getChild(1), MOVRegReg());
 
@@ -3164,7 +3164,7 @@ void OMR::X86::TreeEvaluator::compareGPRegisterToConstantForEquality(TR::Node
 
 TR::Register *OMR::X86::TreeEvaluator::fenceEvaluator(TR::Node *node, TR::CodeGenerator *cg)
    {
-   TR_X86OpCode fenceOp = BADIA32Op;
+   TR::InstOpCode fenceOp = BADIA32Op;
    if (node->isLoadFence() && node->isStoreFence())
       fenceOp.setOpCodeValue(MFENCE);
    else if (node->isLoadFence())
@@ -3738,7 +3738,7 @@ TR::Register *OMR::X86::TreeEvaluator::PrefetchEvaluator(TR::Node *node, TR::Cod
 
    TR::Compilation *comp = cg->comp();
 
-   TR_X86OpCode prefetchOp(BADIA32Op);
+   TR::InstOpCode prefetchOp(BADIA32Op);
 
    static char * disablePrefetch = feGetEnv("TR_DisablePrefetch");
    if (comp->isOptServer() || disablePrefetch)

compiler/x/codegen/OMRX86Instruction.cpp

@@ -1465,7 +1465,7 @@ void padUnresolvedReferenceInstruction(TR::Instruction *instr, TR::MemoryReferen
 
 void insertUnresolvedReferenceInstructionMemoryBarrier(TR::CodeGenerator *cg, int32_t barrier, TR::Instruction *inst, TR::MemoryReference *mr, TR::Register *srcReg, TR::MemoryReference *anotherMr)
    {
-      TR_X86OpCode fenceOp;
+      TR::InstOpCode fenceOp;
       bool is5ByteFence = false;
 
       TR_ASSERT_FATAL(cg->comp()->compileRelocatableCode() || cg->comp()->isOutOfProcessCompilation() || cg->comp()->target().cpu.requiresLFence() == cg->getX86ProcessorInfo().requiresLFENCE(), "requiresLFence() failed\n");
@@ -3267,7 +3267,7 @@ bool TR::X86FPCompareRegRegInstruction::swapOperands()
 
    while (cursor != NULL)
       {
-      TR_X86OpCode  cursorOp = cursor->getOpCode();
+      TR::InstOpCode  cursorOp = cursor->getOpCode();
 
       if (cursorOp.isBranchOp() || cursorOp.isSetRegInstruction())
          break;

compiler/x/codegen/OMRX86Instruction.hpp

@@ -65,7 +65,7 @@ enum TR_X86MemoryBarrierKinds
    LockPrefix           = 0x08
    };
 
-extern int32_t memoryBarrierRequired(TR_X86OpCode &op, TR::MemoryReference *mr, TR::CodeGenerator *cg, bool onlyAskingAboutFences);
+extern int32_t memoryBarrierRequired(TR::InstOpCode &op, TR::MemoryReference *mr, TR::CodeGenerator *cg, bool onlyAskingAboutFences);
 extern int32_t estimateMemoryBarrierBinaryLength(int32_t barrier, TR::CodeGenerator *cg);
 extern void padUnresolvedReferenceInstruction(TR::Instruction *instr, TR::MemoryReference *mr, TR::CodeGenerator *cg);
 extern void insertUnresolvedReferenceInstructionMemoryBarrier(TR::CodeGenerator *cg, int32_t barrier, TR::Instruction *inst, TR::MemoryReference *mr, TR::Register *srcReg = NULL, TR::MemoryReference *anotherMr = NULL);

compiler/x/codegen/OpNames.cpp

@@ -27,13 +27,13 @@
 #include "codegen/InstOpCode.hpp"
 
 const char *
-TR_X86OpCode::getOpCodeName(TR::CodeGenerator *cg)
+TR::InstOpCode::getOpCodeName(TR::CodeGenerator *cg)
    {
    return cg->comp()->getDebug()->getOpCodeName(this);
    }
 
 const char *
-TR_X86OpCode::getMnemonicName(TR::CodeGenerator *cg)
+TR::InstOpCode::getMnemonicName(TR::CodeGenerator *cg)
    {
    return cg->comp()->getDebug()->getMnemonicName(this);
    }

compiler/x/codegen/RestartSnippet.hpp

@@ -61,7 +61,7 @@ class X86RestartSnippet  : public TR::Snippet
 
    uint8_t *genRestartJump(TR_X86OpCodes branchOp, uint8_t *bufferCursor, TR::LabelSymbol *label)
       {
-      TR_X86OpCode  opcode(branchOp);
+      TR::InstOpCode  opcode(branchOp);
 
       uint8_t *destination = label->getCodeLocation();
       intptr_t  distance    = destination - (bufferCursor + 2);

compiler/x/codegen/SubtractAnalyser.cpp

@@ -175,7 +175,7 @@ TR::Register* TR_X86SubtractAnalyser::integerSubtractAnalyserImpl(TR::Node     *
                // Don't do this though if condition codes are needed.  The sequence
                // depends on the carry flag being valid as if a sub was done.
                //
-               bool nodeIs64Bit = TR_X86OpCode(regRegOpCode).hasLongSource();
+               bool nodeIs64Bit = TR::InstOpCode(regRegOpCode).hasLongSource();
                generateRegInstruction(NEGReg(nodeIs64Bit), secondChild, secondRegister, _cg);
                thirdReg       = secondRegister;
                secondRegister = firstRegister;

compiler/x/codegen/X86BinaryEncoding.cpp

@@ -74,7 +74,7 @@ class TR_OpaqueClassBlock;
 class TR_OpaqueMethodBlock;
 
 int32_t memoryBarrierRequired(
-      TR_X86OpCode &op,
+      TR::InstOpCode &op,
       TR::MemoryReference *mr,
       TR::CodeGenerator *cg,
       bool onlyAskingAboutFences)
@@ -169,11 +169,11 @@ int32_t estimateMemoryBarrierBinaryLength(int32_t barrier, TR::CodeGenerator *cg
    if (barrier & LockOR)
       length = 5;
    else if ((barrier & kLoadFence) && cg->comp()->target().cpu.requiresLFence())
-      length = TR_X86OpCode(LFENCE).length();
+      length = TR::InstOpCode(LFENCE).length();
    else if ((barrier & kMemoryFence) == kMemoryFence)
-      length = TR_X86OpCode(MFENCE).length();
+      length = TR::InstOpCode(MFENCE).length();
    else if (barrier & kStoreFence)
-      length = TR_X86OpCode(SFENCE).length();
+      length = TR::InstOpCode(SFENCE).length();
 
    return length;
    }
@@ -1396,13 +1396,13 @@ uint8_t* TR::X86RegInstruction::generateOperand(uint8_t* cursor)
 
 uint8_t TR::X86RegInstruction::getBinaryLengthLowerBound()
    {
-   TR_X86OpCode  &opCode = getOpCode();
+   TR::InstOpCode  &opCode = getOpCode();
    return opCode.length(self()->rexBits());
    }
 
 int32_t TR::X86RegInstruction::estimateBinaryLength(int32_t currentEstimate)
    {
-   TR_X86OpCode  &opCode = getOpCode();
+   TR::InstOpCode  &opCode = getOpCode();
    setEstimatedBinaryLength(opCode.length(self()->rexBits()) + rexRepeatCount());
    return currentEstimate + getEstimatedBinaryLength();
    }

compiler/x/codegen/X86Debug.cpp

@@ -2417,13 +2417,13 @@ static const char * opCodeToMnemonicMap[] =
    };
 
 const char *
-TR_Debug::getOpCodeName(TR_X86OpCode  * opCode)
+TR_Debug::getOpCodeName(TR::InstOpCode  * opCode)
    {
    return opCodeToNameMap[opCode->getOpCodeValue()];
    }
 
 const char *
-TR_Debug::getMnemonicName(TR_X86OpCode  * opCode)
+TR_Debug::getMnemonicName(TR::InstOpCode  * opCode)
    {
    if (_comp->target().isLinux())
       {