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Remove unused f2i,d2i conversion code
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@BradleyWood
BradleyWood committed Jul 7, 2021
1 parent f222cc8 commit d6e5b72
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Showing 2 changed files with 0 additions and 167 deletions.
166 changes: 0 additions & 166 deletions compiler/x/codegen/FPTreeEvaluator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -847,172 +847,6 @@ TR::Register *OMR::X86::TreeEvaluator::i2dEvaluator(TR::Node *node, TR::CodeGene
return target;
}


// General float/double convert to int
//
TR::Register *OMR::X86::TreeEvaluator::fpConvertToInt(TR::Node *node, TR::SymbolReference *helperSymRef, TR::CodeGenerator *cg)
{
TR::Compilation *comp = cg->comp();
TR_ASSERT(cg->comp()->target().is32Bit(), "AMD64 has enableSSE set, so it doesn't use this logic");

TR::Node *child = node->getFirstChild();
TR::Register *accReg = 0;
TR::Register *floatReg;
TR::Register *resultReg;

TR::MemoryReference *tempMR;
TR::X86RegMemInstruction *loadInstr;
TR::RegisterDependencyConditions *deps;

TR::LabelSymbol *startLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *reStartLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *snippetLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);

startLabel->setStartInternalControlFlow();
reStartLabel->setEndInternalControlFlow();

TR_ASSERT_FATAL(cg->comp()->compileRelocatableCode() || cg->comp()->isOutOfProcessCompilation() || cg->comp()->compilePortableCode() || cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE) == cg->getX86ProcessorInfo().supportsSSE(), "supportsSSE() failed\n");
TR_ASSERT_FATAL(cg->comp()->compileRelocatableCode() || cg->comp()->isOutOfProcessCompilation() || cg->comp()->compilePortableCode() || cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE2) == cg->getX86ProcessorInfo().supportsSSE2(), "supportsSSE2() failed\n");

bool optimizeF2IWithSSE = ( node->getOpCodeValue() == TR::f2i &&
cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE) );

bool optimizeD2IWithSSE2 = ( node->getOpCodeValue() == TR::d2i &&
cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE2) );

if (!optimizeF2IWithSSE && !optimizeD2IWithSSE2)
{
floatReg = cg->evaluate(child);
if (floatReg && floatReg->needsPrecisionAdjustment())
{
TR::TreeEvaluator::insertPrecisionAdjustment(floatReg, node, cg);
}
}

generateLabelInstruction(TR::InstOpCode::label, node, startLabel, cg);

if (!optimizeF2IWithSSE && !optimizeD2IWithSSE2)
{
int16_t fpcw;

fpcw = comp->getJittedMethodSymbol()->usesSinglePrecisionMode() ?
SINGLE_PRECISION_ROUND_TO_ZERO : DOUBLE_PRECISION_ROUND_TO_ZERO;

fpcw = comp->getJittedMethodSymbol()->usesSinglePrecisionMode() ?
SINGLE_PRECISION_ROUND_TO_NEAREST : DOUBLE_PRECISION_ROUND_TO_NEAREST;

tempMR = (cg->machine())->getDummyLocalMR(TR::Int32);

generateMemInstruction(TR::InstOpCode::LDCWMem, node, generateX86MemoryReference(cg->findOrCreate2ByteConstant(node, fpcw), cg), cg);
generateFPMemRegInstruction(TR::InstOpCode::FISTMemReg, node, tempMR, floatReg, cg);
generateMemInstruction(TR::InstOpCode::LDCWMem, node, generateX86MemoryReference(cg->findOrCreate2ByteConstant(node, fpcw), cg), cg);
resultReg = cg->allocateRegister();
loadInstr = generateRegMemInstruction(TR::InstOpCode::L4RegMem, node, resultReg, generateX86MemoryReference(*tempMR, 0, cg), cg);
generateRegImmInstruction(TR::InstOpCode::CMP4RegImm4, node, resultReg, INT_MIN, cg);
generateLabelInstruction(TR::InstOpCode::JE4, node, snippetLabel, cg);
}
else
{
if (optimizeF2IWithSSE)
{
if (child->getReferenceCount() == 1 &&
child->getRegister() == 0 &&
child->getOpCode().isMemoryReference())
{
tempMR = generateX86MemoryReference(child, cg);
floatReg = cg->allocateRegister(TR_X87);
generateFPRegMemInstruction(TR::InstOpCode::FLDRegMem, node, floatReg, tempMR, cg);
resultReg = cg->allocateRegister();
loadInstr = generateRegMemInstruction(TR::InstOpCode::CVTTSS2SIReg4Mem, node, resultReg,
generateX86MemoryReference(*tempMR, 0, cg), cg);
tempMR->decNodeReferenceCounts(cg);
}
else
{
tempMR = (cg->machine())->getDummyLocalMR(TR::Float);
floatReg = cg->evaluate(child);
generateFPMemRegInstruction(TR::InstOpCode::FSTMemReg, node, tempMR, floatReg, cg);
resultReg = cg->allocateRegister();
loadInstr = generateRegMemInstruction(TR::InstOpCode::CVTTSS2SIReg4Mem, node, resultReg,
generateX86MemoryReference(*tempMR, 0, cg), cg);
}
}
else if (optimizeD2IWithSSE2)
{
if (child->getReferenceCount() == 1 &&
child->getRegister() == 0 &&
child->getOpCode().isMemoryReference())
{
tempMR = generateX86MemoryReference(child, cg);
floatReg = cg->allocateRegister(TR_X87);
generateFPRegMemInstruction(TR::InstOpCode::DLDRegMem, node, floatReg, tempMR, cg);
resultReg = cg->allocateRegister();
loadInstr = generateRegMemInstruction(TR::InstOpCode::CVTTSD2SIReg4Mem, node, resultReg,
generateX86MemoryReference(*tempMR, 0, cg), cg);
tempMR->decNodeReferenceCounts(cg);
}
else
{
tempMR = (cg->machine())->getDummyLocalMR(TR::Double);
floatReg = cg->evaluate(child);
generateFPMemRegInstruction(TR::InstOpCode::DSTMemReg, node, tempMR, floatReg, cg);
resultReg = cg->allocateRegister();
loadInstr = generateRegMemInstruction(TR::InstOpCode::CVTTSD2SIReg4Mem, node, resultReg,
generateX86MemoryReference(*tempMR, 0, cg), cg);
}
}
else
{
floatReg = cg->evaluate(child);
tempMR = (cg->machine())->getDummyLocalMR(TR::Int32);
generateFPMemRegInstruction(TR::InstOpCode::FISTMemReg, node, tempMR, floatReg, cg);
resultReg = cg->allocateRegister();
loadInstr = generateRegMemInstruction(TR::InstOpCode::L4RegMem, node, resultReg,
generateX86MemoryReference(*tempMR, 0, cg), cg);
}

generateRegImmInstruction(TR::InstOpCode::CMP4RegImm4, node, resultReg, INT_MIN, cg);
generateLabelInstruction(TR::InstOpCode::JE4, node, snippetLabel, cg);

}

// Create the conversion snippet.
//
cg->addSnippet( new (cg->trHeapMemory()) TR::X86FPConvertToIntSnippet(reStartLabel,
snippetLabel,
helperSymRef,
loadInstr,
cg) );

// Make sure the int register(s) is/are assigned to something.
//
if (accReg)
{
deps = generateRegisterDependencyConditions((uint8_t) 0, 2, cg);
deps->addPostCondition(accReg, TR::RealRegister::eax, cg);
deps->addPostCondition(resultReg, TR::RealRegister::NoReg, cg);
}
else
{
deps = generateRegisterDependencyConditions((uint8_t) 0, 1, cg);
deps->addPostCondition(resultReg, TR::RealRegister::NoReg, cg);
}

generateLabelInstruction(TR::InstOpCode::label, node, reStartLabel, deps, cg);

// We want the floating point register to be live through the snippet, so if it is
// not referenced again we must pop it off the stack here.
//
if (cg->decReferenceCount(child) == 0)
{
generateFPSTiST0RegRegInstruction(TR::InstOpCode::FSTRegReg, node, floatReg, floatReg, cg);
}

node->setRegister(resultReg);
return resultReg;
}


// General float/double convert to long
//
TR::Register *OMR::X86::TreeEvaluator::fpConvertToLong(TR::Node *node, TR::SymbolReference *helperSymRef, TR::CodeGenerator *cg)
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1 change: 0 additions & 1 deletion compiler/x/codegen/OMRTreeEvaluator.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -368,7 +368,6 @@ class OMR_EXTENSIBLE TreeEvaluator: public OMR::TreeEvaluator

static TR::Register *loadMemory(TR::Node *node, TR::MemoryReference *sourceMR, TR_RematerializableTypes type, bool markImplicitExceptionPoint, TR::CodeGenerator *cg);
static TR::Register *conversionAnalyser(TR::Node *node, TR::InstOpCode::Mnemonic memoryToRegisterOp, TR::InstOpCode::Mnemonic registerToRegisterOp, TR::CodeGenerator *cg);
static TR::Register *fpConvertToInt(TR::Node *node, TR::SymbolReference *helperSymRef, TR::CodeGenerator *cg);
static TR::Register *fpConvertToLong(TR::Node *node, TR::SymbolReference *helperSymRef, TR::CodeGenerator *cg);
static TR::Register *generateBranchOrSetOnFPCompare(TR::Node *node, TR::Register *accRegister, bool generateBranch, TR::CodeGenerator *cg);
static TR::Register *generateFPCompareResult(TR::Node *node, TR::Register *accRegister, TR::CodeGenerator *cg);
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