Use common bad instruction on ARM

eclipse · Jun 15, 2021 · e4fe8b4 · e4fe8b4
1 parent 04c2abf
commit e4fe8b4
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Showing 8 changed files with 9 additions and 15 deletions.
diff --git a/compiler/arm/codegen/ARMDebug.cpp b/compiler/arm/codegen/ARMDebug.cpp
@@ -761,7 +761,7 @@ TR_Debug::print(TR::FILE *pOutFile, TR::ARMControlFlowInstruction * instr)
          trfprintf(pOutFile, ", ");
          }
       }
-   if (instr->getOpCode2Value() != ARMOp_bad)
+   if (instr->getOpCode2Value() != TR::InstOpCode::bad)
       {
       trfprintf(pOutFile, ", %s", getOpCodeName(&instr->getOpCode2()));
       }

diff --git a/compiler/arm/codegen/ARMInstruction.hpp b/compiler/arm/codegen/ARMInstruction.hpp
@@ -1358,12 +1358,12 @@ class ARMControlFlowInstruction : public TR::Instruction
 
    ARMControlFlowInstruction(TR::Node *node, TR::CodeGenerator *cg) : TR::Instruction(node, cg) {}
    ARMControlFlowInstruction(TR::InstOpCode::Mnemonic  op, TR::Node *node, TR::CodeGenerator *cg)
-      : TR::Instruction(op, node, cg), _numSources(0), _numTargets(0), _label(NULL), _opCode2(ARMOp_bad)
+      : TR::Instruction(op, node, cg), _numSources(0), _numTargets(0), _label(NULL), _opCode2(TR::InstOpCode::bad)
       {
       }
 
    ARMControlFlowInstruction(TR::InstOpCode::Mnemonic  op, TR::Node *node, TR::RegisterDependencyConditions *deps, TR::CodeGenerator *cg)
-      : TR::Instruction(op, node, deps, cg), _numSources(0), _numTargets(0), _label(NULL), _opCode2(ARMOp_bad)
+      : TR::Instruction(op, node, deps, cg), _numSources(0), _numTargets(0), _label(NULL), _opCode2(TR::InstOpCode::bad)
       {
       }
 

diff --git a/compiler/arm/codegen/ARMSystemLinkage.cpp b/compiler/arm/codegen/ARMSystemLinkage.cpp
@@ -467,7 +467,7 @@ void TR::ARMSystemLinkage::createPrologue(TR::Instruction *cursor)
    //
    if (comp()->getOption(TR_EntryBreakPoints))
       {
-      cursor = new (trHeapMemory()) TR::Instruction(cursor, ARMOp_bad, firstNode, cg());
+      cursor = new (trHeapMemory()) TR::Instruction(cursor, TR::InstOpCode::bad, firstNode, cg());
       }
 
    // allocate stack space

diff --git a/compiler/arm/codegen/OMRInstOpCode.cpp b/compiler/arm/codegen/OMRInstOpCode.cpp
@@ -29,14 +29,13 @@ const OMR::ARM::InstOpCode::OpCodeMetaData OMR::ARM::InstOpCode::metadata[NumOpC
 const OMR::ARM::InstOpCode::TR_OpCodeBinaryEntry OMR::ARM::InstOpCode::binaryEncodings[NumOpCodes] =
 {
    0x00000000,  // assocreg
-   0x00000000,  // bad
+   0xE6000010,  // bad
    0x00000000,  // dd
    0x00000000,  // fence
    0x00000000,  // label
    0x00000000,  // proc
    0x00000000,  // retn
    0x00000000,  // vgnop
-   0xE6000010,  // bad
    0x00800000,  // add
    0x00900000,  // add_r
    0x00A00000,  // adc
@@ -207,9 +206,6 @@ const uint32_t OMR::ARM::InstOpCode::properties[NumOpCodes] =
 // vgnop
 0,
 
-// bad
-0,
-
 // add
 ARMOpProp_HasRecordForm,
 

diff --git a/compiler/arm/codegen/OMRInstOpCode.enum b/compiler/arm/codegen/OMRInstOpCode.enum
@@ -26,7 +26,6 @@
 
 #include "compiler/codegen/OMRInstOpCode.enum"
 
-   ARMOp_bad,              //Illegal Opcode
    ARMOp_add,              // Add
    ARMOp_add_r,            // Add with record
    ARMOp_adc,              // Add with carry

diff --git a/compiler/arm/codegen/OMRInstOpCode.enum.temp.defines b/compiler/arm/codegen/OMRInstOpCode.enum.temp.defines
@@ -24,7 +24,6 @@
  * definitions are permitted.
  */
 
-#define ARMOp_bad OMR::InstOpCode::ARMOp_bad
 #define ARMOp_add OMR::InstOpCode::ARMOp_add
 #define ARMOp_add_r OMR::InstOpCode::ARMOp_add_r
 #define ARMOp_adc OMR::InstOpCode::ARMOp_adc

diff --git a/compiler/arm/codegen/OMRInstruction.cpp b/compiler/arm/codegen/OMRInstruction.cpp
@@ -80,7 +80,7 @@ OMR::ARM::Instruction::Instruction(TR::CodeGenerator *cg, TR::InstOpCode::Mnemon
 OMR::ARM::Instruction::Instruction(TR::Node *node, TR::CodeGenerator *cg)
    : OMR::InstructionConnector(cg, TR::InstOpCode::bad, node)
    {
-   self()->setOpCodeValue(ARMOp_bad);
+   self()->setOpCodeValue(TR::InstOpCode::bad);
    self()->setConditionCode(ARMConditionCodeAL);
    self()->setDependencyConditions(NULL);
    }

diff --git a/compiler/arm/codegen/OMRTreeEvaluator.cpp b/compiler/arm/codegen/OMRTreeEvaluator.cpp
@@ -3832,7 +3832,7 @@ TR::Register *OMR::ARM::TreeEvaluator::BBEndEvaluator(TR::Node *node, TR::CodeGe
       if (lastInstruction->getOpCodeValue() == ARMOp_bl
               && lastInstruction->getNode()->getSymbolReference()->getReferenceNumber() == TR_aThrow)
          {
-         lastInstruction = generateInstruction(cg, ARMOp_bad, node, lastInstruction);
+         lastInstruction = generateInstruction(cg, TR::InstOpCode::bad, node, lastInstruction);
          }
       }
    TR::RegisterDependencyConditions *deps = NULL;
@@ -3903,7 +3903,7 @@ TR::Register *OMR::ARM::TreeEvaluator::conversionAnalyser(TR::Node          *nod
 
 static void generateSignOrZeroExtend(TR::Node *node, TR::Register *dst, TR::Register *src, bool needSignExtend, int32_t bitsInDst, TR::CodeGenerator *cg)
    {
-   TR::InstOpCode::Mnemonic opcode = ARMOp_bad;
+   TR::InstOpCode::Mnemonic opcode = TR::InstOpCode::bad;
 
    if (cg->comp()->target().cpu.id() >= TR_ARMv6)
       {
@@ -3932,7 +3932,7 @@ static void generateSignOrZeroExtend(TR::Node *node, TR::Register *dst, TR::Regi
          }
       }
 
-   if (opcode != ARMOp_bad)
+   if (opcode != TR::InstOpCode::bad)
       {
       generateTrg1Src1Instruction(cg, opcode, node, dst, src);
       }