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Replace TR_ARMRegisterDependency with TR::RegisterDependency
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Use the same class as the other architectures as they are functionally
equivalent.

Signed-off-by: Daryl Maier <maier@ca.ibm.com>
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@0xdaryl
0xdaryl committed Nov 9, 2020
1 parent b54a622 commit e866e3c
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Showing 2 changed files with 28 additions and 93 deletions.
30 changes: 15 additions & 15 deletions compiler/arm/codegen/OMRRegisterDependency.cpp
View file
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (c) 2000, 2019 IBM Corp. and others
* Copyright (c) 2000, 2020 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
Expand Down Expand Up @@ -334,8 +334,8 @@ void TR_ARMRegisterDependencyGroup::assignRegisters(TR::Instruction *currentIns
{
for (i = 0; i< numberOfRegisters; i++)
{
virtReg = dependencies[i].getRegister();
dependentRegNum = dependencies[i].getRealRegister();
virtReg = _dependencies[i].getRegister();
dependentRegNum = _dependencies[i].getRealRegister();
if (dependentRegNum == TR::RealRegister::SpilledReg)
{
TR_ASSERT(virtReg->getBackingStorage(),"should have a backing store if dependentRegNum == spillRegIndex()\n");
Expand Down Expand Up @@ -399,11 +399,11 @@ void TR_ARMRegisterDependencyGroup::assignRegisters(TR::Instruction *currentIns
}
for (i = 0; i < numberOfRegisters; i++)
{
virtReg = dependencies[i].getRegister();
virtReg = _dependencies[i].getRegister();

if (virtReg->getAssignedRealRegister()!=NULL)
{
if (dependencies[i].getRealRegister() == TR::RealRegister::NoReg)
if (_dependencies[i].getRealRegister() == TR::RealRegister::NoReg)
{
virtReg->block();
}
Expand All @@ -412,7 +412,7 @@ void TR_ARMRegisterDependencyGroup::assignRegisters(TR::Instruction *currentIns
dependentRegNum = toRealRegister(virtReg->getAssignedRealRegister())->getRegisterNumber();
for (j=0; j<numberOfRegisters; j++)
{
if (dependentRegNum == dependencies[j].getRealRegister())
if (dependentRegNum == _dependencies[j].getRealRegister())
{
virtReg->block();
break;
Expand All @@ -427,8 +427,8 @@ void TR_ARMRegisterDependencyGroup::assignRegisters(TR::Instruction *currentIns
changed = false;
for (i = 0; i < numberOfRegisters; i++)
{
virtReg = dependencies[i].getRegister();
dependentRegNum = dependencies[i].getRealRegister();
virtReg = _dependencies[i].getRegister();
dependentRegNum = _dependencies[i].getRealRegister();
dependentRealReg = machine->getRealRegister(dependentRegNum);

if (dependentRegNum != TR::RealRegister::NoReg &&
Expand All @@ -448,13 +448,13 @@ void TR_ARMRegisterDependencyGroup::assignRegisters(TR::Instruction *currentIns
changed = false;
for (i = 0; i < numberOfRegisters; i++)
{
virtReg = dependencies[i].getRegister();
virtReg = _dependencies[i].getRegister();
assignedRegister = NULL;
if (virtReg->getAssignedRealRegister() != NULL)
{
assignedRegister = toRealRegister(virtReg->getAssignedRealRegister());
}
dependentRegNum = dependencies[i].getRealRegister();
dependentRegNum = _dependencies[i].getRealRegister();
dependentRealReg = machine->getRealRegister(dependentRegNum);
if (dependentRegNum != TR::RealRegister::NoReg &&
dependentRegNum != TR::RealRegister::SpilledReg &&
Expand All @@ -469,12 +469,12 @@ void TR_ARMRegisterDependencyGroup::assignRegisters(TR::Instruction *currentIns

for (i=0; i<numberOfRegisters; i++)
{
if (dependencies[i].getRealRegister() == TR::RealRegister::NoReg)
if (_dependencies[i].getRealRegister() == TR::RealRegister::NoReg)
{
bool excludeGPR0 = dependencies[i].getExcludeGPR0()?true:false;
bool excludeGPR0 = _dependencies[i].getExcludeGPR0()?true:false;
TR::RealRegister *realOne;

virtReg = dependencies[i].getRegister();
virtReg = _dependencies[i].getRegister();
realOne = virtReg->getAssignedRealRegister();
if (realOne!=NULL && excludeGPR0 && toRealRegister(realOne)->getRegisterNumber()==TR::RealRegister::gr0)
{
Expand Down Expand Up @@ -531,7 +531,7 @@ TR::RegisterDependencyConditions *OMR::ARM::RegisterDependencyConditions::clone(
TR::CodeGenerator * cg, TR::RegisterDependencyConditions *added)
{
TR::RegisterDependencyConditions *result;
TR_ARMRegisterDependency *singlePair;
TR::RegisterDependency *singlePair;
int32_t idx, preNum, postNum, addPre=0, addPost=0;
#if defined(DEBUG)
int32_t preGPR=0, postGPR=0;
Expand Down Expand Up @@ -602,7 +602,7 @@ TR::RegisterDependencyConditions *OMR::ARM::RegisterDependencyConditions::cloneA
TR::CodeGenerator * cg, TR::RegisterDependencyConditions *added)
{
TR::RegisterDependencyConditions *result;
TR_ARMRegisterDependency *singlePair;
TR::RegisterDependency *singlePair;
int32_t idx, preNum, postNum, addPre=0, addPost=0;
TR::Register *postReg, *tempReg;
TR::RealRegister::RegNum rnum;
Expand Down
91 changes: 13 additions & 78 deletions compiler/arm/codegen/OMRRegisterDependency.hpp
View file
Expand Up @@ -36,84 +36,19 @@

#include "compiler/codegen/OMRRegisterDependency.hpp"

#include "codegen/RealRegister.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/RegisterDependencyStruct.hpp"
#include "env/IO.hpp"

namespace TR { class Register; }

#define DefinesDependentRegister 0x01
#define ReferencesDependentRegister 0x02
#define UsesDependentRegister (ReferencesDependentRegister | DefinesDependentRegister)
#define ExcludeGPR0InAssigner 0x80

struct TR_ARMRegisterDependency
{
TR::RealRegister::RegNum _realRegister;
uint8_t _flags;
TR::Register *_virtualRegister;

TR::RealRegister::RegNum getRealRegister() {return _realRegister;}
TR::RealRegister::RegNum setRealRegister(TR::RealRegister::RegNum r)
{
return (_realRegister = r);
}

uint32_t getFlags() {return _flags;}
uint32_t assignFlags(uint8_t f) {return _flags = f;}
uint32_t setFlags(uint8_t f) {return (_flags |= f);}
uint32_t resetFlags(uint8_t f) {return (_flags &= ~f);}

uint32_t getDefsRegister() {return _flags & DefinesDependentRegister;}
uint32_t setDefsRegister() {return (_flags |= DefinesDependentRegister);}
uint32_t resetDefsRegister() {return (_flags &= ~DefinesDependentRegister);}

uint32_t getRefsRegister() {return _flags & ReferencesDependentRegister;}
uint32_t setRefsRegister() {return (_flags |= ReferencesDependentRegister);}
uint32_t resetRefsRegister() {return (_flags &= ~ReferencesDependentRegister);}

uint32_t getUsesRegister() {return _flags & UsesDependentRegister;}

uint32_t getExcludeGPR0() {return _flags & ExcludeGPR0InAssigner;}
uint32_t setExcludeGPR0() {return (_flags |= ExcludeGPR0InAssigner);}
uint32_t resetExcludeGPR0() {return (_flags &= ~ExcludeGPR0InAssigner);}

TR::Register *getRegister() {return _virtualRegister;}
TR::Register *setRegister(TR::Register *r) {return (_virtualRegister = r);}

#if 0 // def DEBUG
void print(TR::FILE *pOutFile, TR::CodeGenerator *cg)
{
TR_ARMMachine *machine = getARMMachine(cg);
TR_FrontEnd *fe = cg->comp()->fe();
trfprintf(pOutFile,"\nVirtual: ");
(void)trfflush(pOutFile);
_virtualRegister->print(pOutFile, TR_WordReg);
(void)trfflush(pOutFile);
trfprintf(pOutFile,", Real: ");
(void)trfflush(pOutFile);
if (machine->getRealRegister(_realRegister)==NULL)
{
trfprintf(pOutFile,"NoReg");
(void)trfflush(pOutFile);
}
else
{
machine->getRealRegister(_realRegister)->print(pOutFile, TR_WordReg);
(void)trfflush(pOutFile);
}
trfprintf(pOutFile,", Flags: %x",_flags);
(void)trfflush(pOutFile);
}
#endif

};

#define NUM_DEFAULT_DEPENDENCIES 1

class TR_ARMRegisterDependencyGroup
{
TR_ARMRegisterDependency dependencies[NUM_DEFAULT_DEPENDENCIES];
TR::RegisterDependency _dependencies[NUM_DEFAULT_DEPENDENCIES];

// Use TR_ARMRegisterDependencyGroup::create to allocate an object of this type
//
Expand All @@ -122,7 +57,7 @@ class TR_ARMRegisterDependencyGroup
TR_ASSERT(numDependencies > 0, "operator new called with numDependencies == 0");
if (numDependencies > NUM_DEFAULT_DEPENDENCIES)
{
s += (numDependencies-NUM_DEFAULT_DEPENDENCIES)*sizeof(TR_ARMRegisterDependency);
s += (numDependencies-NUM_DEFAULT_DEPENDENCIES)*sizeof(TR::RegisterDependency);
}
return m->allocateHeapMemory(s);
}
Expand All @@ -138,27 +73,27 @@ class TR_ARMRegisterDependencyGroup
return numDependencies ? new (numDependencies, m) TR_ARMRegisterDependencyGroup : 0;
}

TR_ARMRegisterDependency *getRegisterDependency(uint32_t index)
TR::RegisterDependency *getRegisterDependency(uint32_t index)
{
return &dependencies[index];
return &_dependencies[index];
}

void setDependencyInfo(uint32_t index,
TR::Register *vr,
TR::RealRegister::RegNum rr,
uint8_t flag)
{
dependencies[index].setRegister(vr);
dependencies[index].assignFlags(flag);
dependencies[index].setRealRegister(rr);
_dependencies[index].setRegister(vr);
_dependencies[index].assignFlags(flag);
_dependencies[index].setRealRegister(rr);
}

TR::Register *searchForRegister(TR::RealRegister::RegNum rr, uint32_t numberOfRegisters)
{
for (uint32_t i=0; i<numberOfRegisters; i++)
{
if (dependencies[i].getRealRegister() == rr)
return(dependencies[i].getRegister());
if (_dependencies[i].getRealRegister() == rr)
return(_dependencies[i].getRegister());
}
return(NULL);
}
Expand All @@ -172,15 +107,15 @@ class TR_ARMRegisterDependencyGroup
{
for (uint32_t i = 0; i < numberOfRegisters; i++)
{
dependencies[i].getRegister()->block();
_dependencies[i].getRegister()->block();
}
}

void unblockRegisters(uint32_t numberOfRegisters)
{
for (uint32_t i = 0; i < numberOfRegisters; i++)
{
dependencies[i].getRegister()->unblock();
_dependencies[i].getRegister()->unblock();
}
}
};
Expand Down

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