AArch64: Int32 & Int64 Support for Vector Subtract

This commit accommodates Int32 & Int64 support for vector subtraction operations. Signed-off-by: Md. Alvee Noor <mnoor@unb.ca>
eclipse · Jun 16, 2021 · ea6ff48 · ea6ff48
1 parent 551857c
commit ea6ff48
Show file tree

Hide file tree

Showing 4 changed files with 12 additions and 0 deletions.
diff --git a/compiler/aarch64/codegen/ARM64Debug.cpp b/compiler/aarch64/codegen/ARM64Debug.cpp
@@ -737,6 +737,8 @@ static const char *opCodeToNameMap[] =
    "vfadd2d",
    "vsub16b",
    "vsub8h",
+   "vsub4s",
+   "vsub2d",
    "vfsub4s",
    "vfsub2d",
    "vmul16b",

diff --git a/compiler/aarch64/codegen/BinaryEvaluator.cpp b/compiler/aarch64/codegen/BinaryEvaluator.cpp
@@ -320,6 +320,12 @@ OMR::ARM64::TreeEvaluator::vsubEvaluator(TR::Node *node, TR::CodeGenerator *cg)
       case TR::VectorInt16:
          subOp = TR::InstOpCode::vsub8h;
          break;
+      case TR::VectorInt32:
+         subOp = TR::InstOpCode::vsub4s;
+         break;
+      case TR::VectorInt64:
+         subOp = TR::InstOpCode::vsub2d;
+         break;
       case TR::VectorFloat:
          subOp = TR::InstOpCode::vfsub4s;
          break;

diff --git a/compiler/aarch64/codegen/OMRInstOpCode.enum b/compiler/aarch64/codegen/OMRInstOpCode.enum
@@ -715,6 +715,8 @@
 		vfadd2d,                                                  	/* 0x4E60D400	FADD      	 */
 		vsub16b,                                                  	/* 0x6E208400	SUB      	 */
 		vsub8h,                                                  	/* 0x6E608400	SUB      	 */
+		vsub4s,                                                  	/* 0x6EA08400	SUB      	 */
+		vsub2d,                                                  	/* 0x6EE08400	SUB      	 */
 		vfsub4s,                                                  	/* 0x4EA0D400	FSUB      	 */
 		vfsub2d,                                                  	/* 0x4EE0D400	FSUB      	 */
 		vmul16b,                                                  	/* 0x4E209C00	MUL      	 */

diff --git a/compiler/aarch64/codegen/OpBinary.cpp b/compiler/aarch64/codegen/OpBinary.cpp
@@ -721,6 +721,8 @@ const OMR::ARM64::InstOpCode::OpCodeBinaryEntry OMR::ARM64::InstOpCode::binaryEn
 		0x4E60D400,	/* FADD      	vfadd2d	 */
 		0x6E208400,	/* SUB      	vsub16b	 */
 		0x6E608400,	/* SUB      	vsub8h	 */
+		0x6EA08400,	/* SUB      	vsub4s	 */
+		0x6EE08400,	/* SUB      	vsub2d	 */
 		0x4EA0D400,	/* FSUB      	vfsub4s	 */
 		0x4EE0D400,	/* FSUB      	vfsub2d	 */
 		0x4E209C00,	/* MUL      	vmul16b	 */