Deprecate blockIndex in aarch64 and arm

Related to: #5293 Signed-off-by: Annabelle Huo <Annabelle.Huo@ibm.com>
eclipse · Apr 28, 2021 · ef9fa86 · ef9fa86
1 parent 8b6089f
commit ef9fa86
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Showing 5 changed files with 4 additions and 29 deletions.
diff --git a/compiler/aarch64/codegen/OMRCodeGenerator.cpp b/compiler/aarch64/codegen/OMRCodeGenerator.cpp
@@ -225,8 +225,6 @@ OMR::ARM64::CodeGenerator::doRegisterAssignment(TR_RegisterKinds kindsToAssign)
 
       self()->tracePreRAInstruction(instructionCursor);
 
-      self()->setCurrentBlockIndex(instructionCursor->getBlockIndex());
-
       instructionCursor->assignRegisters(TR_GPR);
 
       // Maintain Internal Control Flow Depth

diff --git a/compiler/aarch64/codegen/OMRInstruction.cpp b/compiler/aarch64/codegen/OMRInstruction.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2018, 2020 IBM Corp. and others
+ * Copyright (c) 2018, 2021 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this
@@ -32,23 +32,20 @@ OMR::ARM64::Instruction::Instruction(TR::CodeGenerator *cg, TR::InstOpCode::Mnem
    : OMR::Instruction(cg, op, node),
      _conditions(NULL)
    {
-   self()->setBlockIndex(cg->getCurrentBlockIndex());
    }
 
 
 OMR::ARM64::Instruction::Instruction(TR::CodeGenerator *cg, TR::Instruction *precedingInstruction, TR::InstOpCode::Mnemonic op, TR::Node *node)
    : OMR::Instruction(cg, precedingInstruction, op, node),
      _conditions(NULL)
    {
-   self()->setBlockIndex(cg->getCurrentBlockIndex());
    }
 
 
 OMR::ARM64::Instruction::Instruction(TR::CodeGenerator *cg, TR::InstOpCode::Mnemonic op, TR::RegisterDependencyConditions *cond, TR::Node *node)
    : OMR::Instruction(cg, op, node),
      _conditions(cond)
    {
-   self()->setBlockIndex(cg->getCurrentBlockIndex());
    if (cond)
       cond->bookKeepingRegisterUses(self(), cg);
    }
@@ -58,7 +55,6 @@ OMR::ARM64::Instruction::Instruction(TR::CodeGenerator *cg, TR::Instruction *pre
    : OMR::Instruction(cg, precedingInstruction, op, node),
      _conditions(cond)
    {
-   self()->setBlockIndex(cg->getCurrentBlockIndex());
    if (cond)
       cond->bookKeepingRegisterUses(self(), cg);
    }

diff --git a/compiler/aarch64/codegen/OMRInstruction.hpp b/compiler/aarch64/codegen/OMRInstruction.hpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2018, 2020 IBM Corp. and others
+ * Copyright (c) 2018, 2021 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this
@@ -159,18 +159,6 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
       return (_conditions = cond);
       }
 
-   /**
-    * @brief Gets the basic block index
-    * @return basic block index
-    */
-   int32_t getBlockIndex()            { return _blockIndex; }
-   /**
-    * @brief Sets the basic block index
-    * @param[in] i : basic block index
-    * @return basic block index
-    */
-   void setBlockIndex(int32_t i)   { _blockIndex = i; }
-
    /**
     * @brief Sets GCMap mask
     * @param[in] cg : CodeGenerator
@@ -252,7 +240,6 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
    void setWillBePatched(bool v = true) { v ? _index |= WillBePatched : _index &= ~WillBePatched; }
 
    private:
-      int32_t _blockIndex;
       TR::RegisterDependencyConditions *_conditions;
    };
 

diff --git a/compiler/arm/codegen/OMRInstruction.cpp b/compiler/arm/codegen/OMRInstruction.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2020 IBM Corp. and others
+ * Copyright (c) 2000, 2021 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this
@@ -67,15 +67,13 @@ OMR::ARM::Instruction::Instruction(TR::CodeGenerator *cg, TR::Instruction *prece
                   _conditions(0),
                   _asyncBranch(false)
    {
-   self()->setBlockIndex(cg->getCurrentBlockIndex());
    }
 
 OMR::ARM::Instruction::Instruction(TR::CodeGenerator *cg, TR::InstOpCode::Mnemonic op, TR::Node *node)
    :OMR::Instruction(cg, op, node),
      _conditions(0),
      _asyncBranch(false)
    {
-   self()->setBlockIndex(cg->getCurrentBlockIndex());
    }
 
 // TODO: need to fix the InstOpCode initialization

diff --git a/compiler/arm/codegen/OMRInstruction.hpp b/compiler/arm/codegen/OMRInstruction.hpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2020 IBM Corp. and others
+ * Copyright (c) 2000, 2021 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this
@@ -91,9 +91,6 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
    TR_ARMOpCodes getRecordFormOpCode()             {return _opcode.getRecordFormOpCodeValue();}
    TR_ARMOpCodes setOpCodeValue(TR_ARMOpCodes op)  {return _opcode.setOpCodeValue(op);}
 
-   int32_t  getBlockIndex()            { return _blockIndex; }
-   void     setBlockIndex(int32_t i)   { _blockIndex = i; }
-
    void ARMNeedsGCMap(uint32_t mask);
 
    TR_ARMConditionCode getConditionCode()                          {return _conditionCode;}
@@ -214,7 +211,6 @@ class OMR_EXTENSIBLE Instruction : public OMR::Instruction
 
    private:
       TR_ARMOpCode   _opcode;
-      int32_t       _blockIndex;
       TR_ARMConditionCode                  _conditionCode;
       TR::RegisterDependencyConditions *_conditions;
       bool        _asyncBranch;