Prefix x86 parameterized instruction mnemonic usages with TR::InstOpC…

…ode::
eclipse · Jun 15, 2021 · f7368dd · f7368dd
1 parent 0b28027
commit f7368dd
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Showing 36 changed files with 529 additions and 528 deletions.
diff --git a/compiler/x/amd64/codegen/AMD64SystemLinkage.cpp b/compiler/x/amd64/codegen/AMD64SystemLinkage.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2020 IBM Corp. and others
+ * Copyright (c) 2000, 2021 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this

diff --git a/compiler/x/amd64/codegen/OMRCodeGenerator.cpp b/compiler/x/amd64/codegen/OMRCodeGenerator.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2020 IBM Corp. and others
+ * Copyright (c) 2000, 2021 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this

diff --git a/compiler/x/amd64/codegen/OMRMemoryReference.cpp b/compiler/x/amd64/codegen/OMRMemoryReference.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2020 IBM Corp. and others
+ * Copyright (c) 2000, 2021 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this

diff --git a/compiler/x/codegen/BinaryCommutativeAnalyser.cpp b/compiler/x/codegen/BinaryCommutativeAnalyser.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2020 IBM Corp. and others
+ * Copyright (c) 2000, 2021 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this
@@ -892,15 +892,15 @@ TR::Register *TR_X86BinaryCommutativeAnalyser::integerAddAnalyserImpl(TR::Node
       // if eflags are required then we cannot use LEA as it doesn't set or use them
       if (needsEflags || (carry != 0))
          {
-         generateRegRegInstruction(MOVRegReg(is64Bit), root, tempReg, firstRegister, _cg);
+         generateRegRegInstruction(TR::InstOpCode::MOVRegReg(is64Bit), root, tempReg, firstRegister, _cg);
          generateRegRegInstruction(regRegOpCode, root, tempReg, secondRegister, _cg);
          }
       else
          {
          TR::MemoryReference  *tempMR = generateX86MemoryReference(_cg);
          tempMR->setBaseRegister(firstRegister);
          tempMR->setIndexRegister(secondRegister);
-         generateRegMemInstruction(LEARegMem(is64Bit), root, tempReg, tempMR, _cg);
+         generateRegMemInstruction(TR::InstOpCode::LEARegMem(is64Bit), root, tempReg, tempMR, _cg);
          }
       }
    else if (getOpReg1Mem2())

diff --git a/compiler/x/codegen/BinaryEvaluator.cpp b/compiler/x/codegen/BinaryEvaluator.cpp
diff --git a/compiler/x/codegen/CompareAnalyser.cpp b/compiler/x/codegen/CompareAnalyser.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2019 IBM Corp. and others
+ * Copyright (c) 2000, 2021 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this

diff --git a/compiler/x/codegen/ControlFlowEvaluator.cpp b/compiler/x/codegen/ControlFlowEvaluator.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2020 IBM Corp. and others
+ * Copyright (c) 2000, 2021 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this
@@ -706,7 +706,7 @@ void OMR::X86::TreeEvaluator::compareIntegersForEquality(TR::Node *node, TR::Cod
                         cg->stopUsingRegister(tempReg);
                         }
                      else
-                        generateMemImmInstruction(TESTMemImm4(is64Bit), node, tempMR, static_cast<int32_t>(mask), cg);
+                        generateMemImmInstruction(TR::InstOpCode::TESTMemImm4(is64Bit), node, tempMR, static_cast<int32_t>(mask), cg);
                      tempMR->decNodeReferenceCounts(cg);
                      }
                   else
@@ -734,7 +734,7 @@ void OMR::X86::TreeEvaluator::compareIntegersForEquality(TR::Node *node, TR::Cod
                         (andSecondChild->getSize() == 1))
                         testInstr = TR::InstOpCode::TEST1RegImm1;
                      else
-                        testInstr = TESTRegImm4(is64Bit);
+                        testInstr = TR::InstOpCode::TESTRegImm4(is64Bit);
                      generateRegImmInstruction(testInstr, node, tempReg, static_cast<int32_t>(mask), cg);
                      }
                   if (conversionSkipped)
@@ -766,9 +766,9 @@ void OMR::X86::TreeEvaluator::compareIntegersForEquality(TR::Node *node, TR::Cod
                      }
                   else
                      {
-                     testRRInstr = TESTRegReg(is64Bit);
-                     testMRInstr = TESTMemReg(is64Bit);
-                     movRRInstr = MOVRegReg(is64Bit);
+                     testRRInstr = TR::InstOpCode::TESTRegReg(is64Bit);
+                     testMRInstr = TR::InstOpCode::TESTMemReg(is64Bit);
+                     movRRInstr = TR::InstOpCode::MOVRegReg(is64Bit);
                      }
                   temp.genericAnalyser(firstChild, testRRInstr, testMRInstr, movRRInstr, true);
                   }
@@ -925,7 +925,7 @@ void OMR::X86::TreeEvaluator::compareIntegersForEquality(TR::Node *node, TR::Cod
             }
          else
             {
-            cmpInstruction = generateRegImmInstruction(CMPRegImm4(is64Bit), node, firstChildReg, static_cast<int32_t>(constValue), cg);
+            cmpInstruction = generateRegImmInstruction(TR::InstOpCode::CMPRegImm4(is64Bit), node, firstChildReg, static_cast<int32_t>(constValue), cg);
             }
          TR::Symbol *symbol = NULL;
          if (node && secondChild->getOpCode().hasSymbolReference())
@@ -995,9 +995,9 @@ void OMR::X86::TreeEvaluator::compareIntegersForEquality(TR::Node *node, TR::Cod
          }
       else
          {
-         cmpRRInstr = CMPRegReg(is64Bit);
-         cmpRMInstr = CMPRegMem(is64Bit);
-         cmpMRInstr = CMPMemReg(is64Bit);
+         cmpRRInstr = TR::InstOpCode::CMPRegReg(is64Bit);
+         cmpRMInstr = TR::InstOpCode::CMPRegMem(is64Bit);
+         cmpMRInstr = TR::InstOpCode::CMPMemReg(is64Bit);
          }
       temp.integerCompareAnalyser(node, cmpRRInstr, cmpRMInstr, cmpMRInstr);
 
@@ -1070,7 +1070,7 @@ void OMR::X86::TreeEvaluator::compareIntegersForOrder(
          firstChild,
          secondChild,
          false,
-         CMPRegReg(is64Bit), CMPRegMem(is64Bit), CMPMemReg(is64Bit));
+         TR::InstOpCode::CMPRegReg(is64Bit), TR::InstOpCode::CMPRegMem(is64Bit), TR::InstOpCode::CMPMemReg(is64Bit));
       }
    }
 
@@ -1328,22 +1328,22 @@ TR::Register *OMR::X86::TreeEvaluator::iselectEvaluator(TR::Node *node, TR::Code
       TR::TreeEvaluator::compareIntegersForEquality(condition, cg);
       //if ((conditionOp == TR::icmpeq) || (conditionOp == TR::lcmpeq))
       if (conditionOp.isCompareTrueIfEqual())
-         generateRegRegInstruction(CMOVNERegReg(trueValIs64Bit), node, trueReg, falseReg, cg);
+         generateRegRegInstruction(TR::InstOpCode::CMOVNERegReg(trueValIs64Bit), node, trueReg, falseReg, cg);
       else
-         generateRegRegInstruction(CMOVERegReg(trueValIs64Bit), node, trueReg, falseReg, cg);
+         generateRegRegInstruction(TR::InstOpCode::CMOVERegReg(trueValIs64Bit), node, trueReg, falseReg, cg);
       }
    else if (!longCompareOn32bit && conditionOp.isCompareForOrder() && condition->getFirstChild()->getOpCode().isIntegerOrAddress())
       {
       TR::TreeEvaluator::compareIntegersForOrder(condition, cg);
       generateRegRegInstruction((conditionOp.isCompareTrueIfEqual()) ?
-                   ((conditionOp.isCompareTrueIfGreater()) ? CMOVLRegReg(trueValIs64Bit) : CMOVGRegReg(trueValIs64Bit)) :
-                   ((conditionOp.isCompareTrueIfGreater()) ? CMOVLERegReg(trueValIs64Bit) : CMOVGERegReg(trueValIs64Bit)), node, trueReg, falseReg, cg);
+                   ((conditionOp.isCompareTrueIfGreater()) ? TR::InstOpCode::CMOVLRegReg(trueValIs64Bit) : TR::InstOpCode::CMOVGRegReg(trueValIs64Bit)) :
+                   ((conditionOp.isCompareTrueIfGreater()) ? TR::InstOpCode::CMOVLERegReg(trueValIs64Bit) : TR::InstOpCode::CMOVGERegReg(trueValIs64Bit)), node, trueReg, falseReg, cg);
       }
    else
       {
       TR::Register *condReg  = cg->evaluate(condition);
       generateRegRegInstruction(TR::InstOpCode::TEST4RegReg, node, condReg, condReg, cg); // condition is always an int
-      generateRegRegInstruction(CMOVERegReg(trueValIs64Bit), node, trueReg, falseReg, cg);
+      generateRegRegInstruction(TR::InstOpCode::CMOVERegReg(trueValIs64Bit), node, trueReg, falseReg, cg);
       }
 
    if (node->getOpCodeValue() == TR::bselect &&

diff --git a/compiler/x/codegen/DivideCheckSnippet.cpp b/compiler/x/codegen/DivideCheckSnippet.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2019 IBM Corp. and others
+ * Copyright (c) 2000, 2021 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this
@@ -44,7 +44,7 @@ uint8_t *TR::X86DivideCheckSnippet::emitSnippetBody()
    // CMP realDivisorReg, -1
    //
    uint8_t rexPrefix = cg()->comp()->target().is64Bit() ? realDivisorReg->rexBits(TR::RealRegister::REX_B, false) : 0;
-   buffer = TR::InstOpCode(CMPRegImms(_divOp.isLong())).binary(buffer, rexPrefix);
+   buffer = TR::InstOpCode(TR::InstOpCode::CMPRegImms(_divOp.isLong())).binary(buffer, rexPrefix);
    realDivisorReg->setRMRegisterFieldInModRM(buffer-1);
    *buffer++ = -1;
 

diff --git a/compiler/x/codegen/FPBinaryArithmeticAnalyser.cpp b/compiler/x/codegen/FPBinaryArithmeticAnalyser.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2019 IBM Corp. and others
+ * Copyright (c) 2000, 2021 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this

diff --git a/compiler/x/codegen/FPCompareAnalyser.cpp b/compiler/x/codegen/FPCompareAnalyser.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2019 IBM Corp. and others
+ * Copyright (c) 2000, 2021 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this

diff --git a/compiler/x/codegen/FPTreeEvaluator.cpp b/compiler/x/codegen/FPTreeEvaluator.cpp
@@ -444,8 +444,8 @@ TR::Register *OMR::X86::TreeEvaluator::floatingPointStoreEvaluator(TR::Node *nod
       {
       TR::Register *tempRegister = cg->allocateRegister(TR_GPR);
       TR::MemoryReference  *loadMR = generateX86MemoryReference(valueChild, cg);
-      generateRegMemInstruction(LRegMem(nodeIs64Bit), node, tempRegister, loadMR, cg);
-      exceptionPoint = generateMemRegInstruction(SMemReg(nodeIs64Bit), node, tempMR, tempRegister, cg);
+      generateRegMemInstruction(TR::InstOpCode::LRegMem(nodeIs64Bit), node, tempRegister, loadMR, cg);
+      exceptionPoint = generateMemRegInstruction(TR::InstOpCode::SMemReg(nodeIs64Bit), node, tempMR, tempRegister, cg);
       cg->stopUsingRegister(tempRegister);
       loadMR->decNodeReferenceCounts(cg);
       }
@@ -462,7 +462,7 @@ TR::Register *OMR::X86::TreeEvaluator::floatingPointStoreEvaluator(TR::Node *nod
                {
                // The 64-bit static case does not require the LEA instruction as we can resolve the address in the MOV reg, imm  instruction preceeding the store.
                //
-               exceptionPoint = generateMemRegInstruction(MOVSMemReg(nodeIs64Bit), node, tempMR, sourceRegister, cg);
+               exceptionPoint = generateMemRegInstruction(TR::InstOpCode::MOVSMemReg(nodeIs64Bit), node, tempMR, sourceRegister, cg);
                }
             else
                {
@@ -475,7 +475,7 @@ TR::Register *OMR::X86::TreeEvaluator::floatingPointStoreEvaluator(TR::Node *nod
                generateRegMemInstruction(TR::InstOpCode::LEA8RegMem, node, memReg, tempMR, cg);
                TR::MemoryReference *mr = generateX86MemoryReference(memReg, 0, cg);
                TR_ASSERT(nodeIs64Bit != sourceRegister->isSinglePrecision(), "Wrong operand type to floating point store\n");
-               exceptionPoint = generateMemRegInstruction(MOVSMemReg(nodeIs64Bit), node, mr, sourceRegister, cg);
+               exceptionPoint = generateMemRegInstruction(TR::InstOpCode::MOVSMemReg(nodeIs64Bit), node, mr, sourceRegister, cg);
 
                tempMR->setProcessAsFPVolatile();
 
@@ -490,7 +490,7 @@ TR::Register *OMR::X86::TreeEvaluator::floatingPointStoreEvaluator(TR::Node *nod
          else
             {
             TR_ASSERT(nodeIs64Bit != sourceRegister->isSinglePrecision(), "Wrong operand type to floating point store\n");
-            exceptionPoint = generateMemRegInstruction(MOVSMemReg(nodeIs64Bit), node, tempMR, sourceRegister, cg);
+            exceptionPoint = generateMemRegInstruction(TR::InstOpCode::MOVSMemReg(nodeIs64Bit), node, tempMR, sourceRegister, cg);
             }
          }
       else
@@ -1463,13 +1463,13 @@ TR::Register *OMR::X86::TreeEvaluator::f2iEvaluator(TR::Node *node, TR::CodeGene
                                 generateX86MemoryReference(doubleSource ? cg->findOrCreate8ByteConstant(node, 0) : cg->findOrCreate4ByteConstant(node, 0), cg),
                                 cg);
       // load max int if source is positive, note that for long case, LLONG_MAX << 1 is loaded as it will be shifted right
-      generateRegMemInstruction(CMOVARegMem(longTarget),
+      generateRegMemInstruction(TR::InstOpCode::CMOVARegMem(longTarget),
                                 node,
                                 targetRegister,
                                 generateX86MemoryReference(longTarget ? cg->findOrCreate8ByteConstant(node, LLONG_MAX << 1) : cg->findOrCreate4ByteConstant(node, INT_MAX), cg),
                                 cg);
       // load zero if source is NaN
-      generateRegMemInstruction(CMOVPRegMem(longTarget),
+      generateRegMemInstruction(TR::InstOpCode::CMOVPRegMem(longTarget),
                                 node,
                                 targetRegister,
                                 generateX86MemoryReference(longTarget ? cg->findOrCreate8ByteConstant(node, 0) : cg->findOrCreate4ByteConstant(node, 0), cg),

diff --git a/compiler/x/codegen/IA32LinkageUtils.cpp b/compiler/x/codegen/IA32LinkageUtils.cpp
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2000, 2020 IBM Corp. and others
+ * Copyright (c) 2000, 2021 IBM Corp. and others
  *
  * This program and the accompanying materials are made available under
  * the terms of the Eclipse Public License 2.0 which accompanies this