Merge pull request #7356 from 0xdaryl/cpuid.fix

Refine processor recognition for Intel Cascade Lake and Cooper Lake
eclipse · Jun 3, 2024 · fc58b29 · fc58b29
2 parents a98f362 + ec76a50
commit fc58b29
Show file tree

Hide file tree

Showing 6 changed files with 30 additions and 6 deletions.
diff --git a/compiler/env/ProcessorInfo.hpp b/compiler/env/ProcessorInfo.hpp
@@ -265,9 +265,10 @@ enum TR_ProcessorDescription
    TR_ProcessorIntelBroadwell      = 0x00000010,
    TR_ProcessorIntelSkylake        = 0x00000011,
    TR_ProcessorIntelCascadeLake    = 0x00000012,
-   TR_ProcessorIntelIceLake        = 0x00000013,
-   TR_ProcessorIntelSapphireRapids = 0x00000014,
-   TR_ProcessorIntelEmeraldRapids  = 0x00000015,
+   TR_ProcessorIntelCooperLake     = 0x00000013,
+   TR_ProcessorIntelIceLake        = 0x00000014,
+   TR_ProcessorIntelSapphireRapids = 0x00000015,
+   TR_ProcessorIntelEmeraldRapids  = 0x00000016,
    };
 
 #endif
diff --git a/compiler/x/codegen/OMRCodeGenerator.cpp b/compiler/x/codegen/OMRCodeGenerator.cpp
@@ -182,10 +182,14 @@ void TR_X86ProcessorInfo::initialize(bool force)
                case 0x7e:  // IceLake_L
                   _processorDescription |= TR_ProcessorIntelIceLake; break;
                case 0x55:  // Skylake_X
-                  if (processorStepping == 7)
+                  if (processorStepping >= 5 && processorStepping <= 7)
                      {
                      _processorDescription |= TR_ProcessorIntelCascadeLake;
                      }
+                  else if (processorStepping >= 0xa && processorStepping <= 0xb)
+                     {
+                     _processorDescription |= TR_ProcessorIntelCooperLake;
+                     }
                   else
                      {
                      _processorDescription |= TR_ProcessorIntelSkylake;

diff --git a/compiler/x/codegen/OMRCodeGenerator.hpp b/compiler/x/codegen/OMRCodeGenerator.hpp
@@ -208,6 +208,7 @@ struct TR_X86ProcessorInfo
    bool isIntelBroadwell()      { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelBroadwell; }
    bool isIntelSkylake()        { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelSkylake; }
    bool isIntelCascadeLake()    { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelCascadeLake; }
+   bool isIntelCooperLake()     { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelCooperLake; }
    bool isIntelIceLake()        { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelIceLake; }
    bool isIntelSapphireRapids() { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelSapphireRapids; }
    bool isIntelEmeraldRapids()  { return (_processorDescription & 0x000000ff) == TR_ProcessorIntelEmeraldRapids; }

diff --git a/compiler/x/env/OMRCPU.cpp b/compiler/x/env/OMRCPU.cpp
@@ -291,6 +291,8 @@ OMR::X86::CPU::is_test(OMRProcessorArchitecture p)
          return TR::CodeGenerator::getX86ProcessorInfo().isIntelSkylake() == (_processorDescription.processor == p);
       case OMR_PROCESSOR_X86_INTEL_CASCADELAKE:
          return TR::CodeGenerator::getX86ProcessorInfo().isIntelCascadeLake() == (_processorDescription.processor == p);
+      case OMR_PROCESSOR_X86_INTEL_COOPERLAKE:
+         return TR::CodeGenerator::getX86ProcessorInfo().isIntelCooperLake() == (_processorDescription.processor == p);
       case OMR_PROCESSOR_X86_INTEL_ICELAKE:
          return TR::CodeGenerator::getX86ProcessorInfo().isIntelIceLake() == (_processorDescription.processor == p);
       case OMR_PROCESSOR_X86_INTEL_SAPPHIRERAPIDS:
@@ -466,6 +468,9 @@ OMR::X86::CPU::is_old_api(OMRProcessorArchitecture p)
       case OMR_PROCESSOR_X86_INTEL_CASCADELAKE:
          ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelCascadeLake();
          break;
+      case OMR_PROCESSOR_X86_INTEL_COOPERLAKE:
+         ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelCooperLake();
+         break;
       case OMR_PROCESSOR_X86_INTEL_ICELAKE:
          ans = TR::CodeGenerator::getX86ProcessorInfo().isIntelIceLake();
          break;
@@ -709,6 +714,10 @@ OMR::X86::CPU::getProcessorName()
          returnString = "X86 Intel Cascade Lake";
          break;
 
+      case OMR_PROCESSOR_X86_INTEL_COOPERLAKE:
+         returnString = "X86 Intel Cooper Lake";
+         break;
+
       case OMR_PROCESSOR_X86_INTEL_ICELAKE:
          returnString = "X86 Intel Ice Lake";
          break;

diff --git a/include_core/omrport.h b/include_core/omrport.h
@@ -1466,6 +1466,7 @@ typedef enum OMRProcessorArchitecture {
 	OMR_PROCESSOR_X86_INTEL_BROADWELL,
 	OMR_PROCESSOR_X86_INTEL_SKYLAKE,
 	OMR_PROCESSOR_X86_INTEL_CASCADELAKE,
+	OMR_PROCESSOR_X86_INTEL_COOPERLAKE,
 	OMR_PROCESSOR_X86_INTEL_ICELAKE,
 	OMR_PROCESSOR_X86_INTEL_SAPPHIRERAPIDS,
 	OMR_PROCESSOR_X86_INTEL_EMERALDRAPIDS,

diff --git a/port/common/omrsysinfo_helpers.c b/port/common/omrsysinfo_helpers.c
@@ -104,7 +104,10 @@
 #define CPUID_MODELCODE_INTEL_CORE2_HARPERTOWN            0x17
 #define CPUID_MODELCODE_INTEL_CORE2_WOODCREST_CLOVERTOWN  0x0F
 
-#define CPUID_STEPPING_INTEL_CASCADELAKE                  0x07
+#define CPUID_STEPPING_INTEL_CASCADELAKE_MIN              0x05
+#define CPUID_STEPPING_INTEL_CASCADELAKE_MAX              0x07
+#define CPUID_STEPPING_INTEL_COOPERLAKE_MIN               0x0a
+#define CPUID_STEPPING_INTEL_COOPERLAKE_MAX               0x0b
 
 #define CPUID_FAMILYCODE_AMD_KSERIES                      0x05
 #define CPUID_FAMILYCODE_AMD_ATHLON                       0x06
@@ -311,9 +314,14 @@ omrsysinfo_get_x86_description(struct OMRPortLibrary *portLibrary, OMRProcessorD
 			case CPUID_MODELCODE_INTEL_SKYLAKE_X:
 			case CPUID_MODELCODE_INTEL_SKYLAKE_L:
 			case CPUID_MODELCODE_INTEL_SKYLAKE:
-				if (CPUID_STEPPING_INTEL_CASCADELAKE == processorStepping) {
+				if ((CPUID_STEPPING_INTEL_CASCADELAKE_MIN <= processorStepping) &&
+				    (CPUID_STEPPING_INTEL_CASCADELAKE_MAX >= processorStepping)) {
 					desc->processor = OMR_PROCESSOR_X86_INTEL_CASCADELAKE;
 				}
+				else if ((CPUID_STEPPING_INTEL_COOPERLAKE_MIN <= processorStepping) &&
+				         (CPUID_STEPPING_INTEL_COOPERLAKE_MAX >= processorStepping)) {
+					desc->processor = OMR_PROCESSOR_X86_INTEL_COOPERLAKE;
+				}
 				else {
 					desc->processor = OMR_PROCESSOR_X86_INTEL_SKYLAKE;
 				}