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Deprecate TR_ARMOpCodes in favour of TR::InstOpCode::Mnemonic
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@fjeremic
fjeremic committed Jun 8, 2021
1 parent b50d71b commit fe2f0b5
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Showing 26 changed files with 201 additions and 203 deletions.
6 changes: 3 additions & 3 deletions compiler/arm/codegen/ARMDebug.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -628,7 +628,7 @@ TR_Debug::print(TR::FILE *pOutFile, TR::ARMMemSrc1Instruction * instr)
instr->getMemoryReference()->hasDelayedOffset() &&
!instr->getMemoryReference()->getUnresolvedSnippet())
{
TR_ARMOpCodes op = instr->getOpCodeValue();
TR::InstOpCode::Mnemonic op = instr->getOpCodeValue();
int32_t offset = instr->getMemoryReference()->getOffset();
if(op == ARMOp_strh && !constantIsUnsignedImmed8(offset))
{
Expand Down Expand Up @@ -683,7 +683,7 @@ TR_Debug::print(TR::FILE *pOutFile, TR::ARMTrg1MemInstruction * instr)
instr->getMemoryReference()->hasDelayedOffset() &&
!instr->getMemoryReference()->getUnresolvedSnippet())
{
TR_ARMOpCodes op = instr->getOpCodeValue();
TR::InstOpCode::Mnemonic op = instr->getOpCodeValue();
int32_t offset = instr->getMemoryReference()->getOffset();
if(op == ARMOp_add && instr->getMemoryReference()->getIndexRegister())
{
Expand Down Expand Up @@ -1529,7 +1529,7 @@ TR_Debug::printARMDelayedOffsetInstructions(TR::FILE *pOutFile, TR::ARMMemInstru
bool regSpilled;
uint8_t *bufferPos = instr->getBinaryEncoding();
int32_t offset = instr->getMemoryReference()->getOffset();
TR_ARMOpCodes op = instr->getOpCodeValue();
TR::InstOpCode::Mnemonic op = instr->getOpCodeValue();
TR::RealRegister *base = toRealRegister(instr->getMemoryReference()->getBaseRegister());

intParts localVal(offset);
Expand Down
50 changes: 25 additions & 25 deletions compiler/arm/codegen/ARMGenerateInstructions.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@


TR::Instruction *generateInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Instruction *prev)
{
Expand All @@ -36,7 +36,7 @@ TR::Instruction *generateInstruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateAdminInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Node *fenceNode,
TR::Instruction *prev)
Expand All @@ -48,7 +48,7 @@ TR::Instruction *generateAdminInstruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateAdminInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::RegisterDependencyConditions *cond,
TR::Node *fenceNode,
Expand All @@ -61,7 +61,7 @@ TR::Instruction *generateAdminInstruction(TR::CodeGenerator *c
}

TR::Instruction *generateImmInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
uint32_t imm,
TR::RegisterDependencyConditions *cond,
Expand All @@ -75,7 +75,7 @@ TR::Instruction *generateImmInstruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateImmInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
uint32_t imm,
TR::Instruction *prev)
Expand All @@ -88,7 +88,7 @@ TR::Instruction *generateImmInstruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateImmInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
uint32_t imm,
TR_ExternalRelocationTargetKind relocationKind,
Expand All @@ -101,7 +101,7 @@ TR::Instruction *generateImmInstruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateImmInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
uint32_t imm,
TR_ExternalRelocationTargetKind relocationKind,
Expand All @@ -115,7 +115,7 @@ TR::Instruction *generateImmInstruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateImmSymInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
uint32_t imm,
TR::RegisterDependencyConditions *cond,
Expand All @@ -131,7 +131,7 @@ TR::Instruction *generateImmSymInstruction(TR::CodeGenerator *
}

TR::Instruction *generateMemSrc1Instruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::MemoryReference *mf,
TR::Register *sreg,
Expand All @@ -152,7 +152,7 @@ TR::Instruction *generateMemSrc1Instruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateTrg1MemInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *treg,
TR::MemoryReference *mf,
Expand All @@ -173,7 +173,7 @@ TR::Instruction *generateTrg1MemInstruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateTrg1MemSrc1Instruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *treg,
TR::MemoryReference *mf,
Expand All @@ -187,7 +187,7 @@ TR::Instruction *generateTrg1MemSrc1Instruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateTrg1ImmInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *treg,
uint32_t base,
Expand All @@ -202,7 +202,7 @@ TR::Instruction *generateTrg1ImmInstruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateSrc1ImmInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *s1reg,
uint32_t base,
Expand All @@ -228,7 +228,7 @@ TR::Instruction *generateSrc1ImmInstruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateSrc2Instruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *s1reg,
TR::Register *s2reg,
Expand All @@ -253,7 +253,7 @@ TR::Instruction *generateSrc2Instruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateTrg1Src1Instruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *treg,
TR_ARMOperand2 *s1op,
Expand All @@ -266,7 +266,7 @@ TR::Instruction *generateTrg1Src1Instruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateTrg1Src1Instruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *treg,
TR::Register *s1reg,
Expand All @@ -291,7 +291,7 @@ TR::Instruction *generateTrg1Src1Instruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateTrg1Src1ImmInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *treg,
TR::Register *s1reg,
Expand Down Expand Up @@ -319,7 +319,7 @@ TR::Instruction *generateLoadStartPCInstruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateTrg1Src2Instruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *treg,
TR::Register *s1reg,
Expand All @@ -333,7 +333,7 @@ TR::Instruction *generateTrg1Src2Instruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateTrg1Src2Instruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *treg,
TR::Register *s1reg,
Expand Down Expand Up @@ -361,7 +361,7 @@ TR::Instruction *generateTrg1Src2Instruction(TR::CodeGenerator *cg,

#if (defined(__VFP_FP__) && !defined(__SOFTFP__))
TR::Instruction *generateTrg2Src1Instruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *t1reg,
TR::Register *t2reg,
Expand All @@ -376,7 +376,7 @@ TR::Instruction *generateTrg2Src1Instruction(TR::CodeGenerator *cg,
#endif

TR::Instruction *generateTrg1Src2MulInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *treg,
TR::Register *s1reg,
Expand All @@ -390,7 +390,7 @@ TR::Instruction *generateTrg1Src2MulInstruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateTrg2Src2MulInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::Register *tregHi,
TR::Register *tregLo,
Expand Down Expand Up @@ -454,7 +454,7 @@ TR::Instruction *generateShiftRightByRegister(TR::CodeGenerator *cg,
}

TR::Instruction *generateLabelInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::LabelSymbol *sym,
TR::Instruction *prev,
Expand All @@ -468,7 +468,7 @@ TR::Instruction *generateLabelInstruction(TR::CodeGenerator *cg,
}

TR::Instruction *generateLabelInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::LabelSymbol *sym,
TR::RegisterDependencyConditions *cond,
Expand Down Expand Up @@ -506,7 +506,7 @@ TR::Instruction *generateConditionalBranchInstruction(TR::CodeGenerator
}

TR::ARMControlFlowInstruction *generateControlFlowInstruction(TR::CodeGenerator *cg,
TR_ARMOpCodes op,
TR::InstOpCode::Mnemonic op,
TR::Node *node,
TR::RegisterDependencyConditions *cond)
{
Expand Down
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