add sign injection instructions

edadma · Apr 3, 2018 · 012334e · 012334e
1 parent 93b1e76
commit 012334e
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Showing 4 changed files with 35 additions and 1 deletion.
diff --git a/src/main/scala/CPU.scala b/src/main/scala/CPU.scala
@@ -184,6 +184,7 @@ class CPU( private [riscv] val memory: Memory ) {
       "----- aaaaa 011 ddddd 0000111" -> ((operands: Map[Char, Int]) => new FLD( operands('a'), operands('d') )),
       "bbbbb aaaaa 011 ----- 0100111" -> ((operands: Map[Char, Int]) => new FSD( operands('a'), operands('b') )),
       "bbbbb aaaaa rrr ddddd 1000011" -> ((operands: Map[Char, Int]) => new FMADD( operands('a'), operands('b'), operands('d'), operands('r') )),
+      "bbbbb aaaaa mmm ddddd 1010011" -> ((operands: Map[Char, Int]) => new FP( operands('a'), operands('b'), operands('d'), operands('m') )),
     ) )
 
   // RV32C

diff --git a/src/main/scala/Instruction.scala b/src/main/scala/Instruction.scala
@@ -25,6 +25,7 @@ abstract class RTypeInstruction( mnemonic: Map[Int, String] ) extends Instructio
     }
 
   def disassemble( cpu: CPU ) = s"${mnemonic(funct( cpu ))} x$rd, x$rs1, x$rs2"
+
 }
 
 abstract class R4TypeInstruction( mnemonic: String ) extends Instruction {
@@ -59,6 +60,21 @@ abstract class FRTypeInstruction( f: Int, m: String ) extends RTypeInstruction(
 
 }
 
+abstract class FloatRTypeInstruction( mnemonic: Map[Int, String] ) extends Instruction {
+
+  val rs2: Int
+  val rs1: Int
+  val mode: Int
+  val rd: Int
+
+  def funct( cpu: CPU ) = cpu.instruction >>> 27
+
+  def fmt( cpu: CPU ) = (cpu.instruction >> 25)&3
+
+  def disassemble( cpu: CPU ) = s"${mnemonic(funct( cpu ))} x$rd, x$rs1, x$rs2"
+
+}
+
 abstract class ITypeInstruction( mnemonic: String ) extends Instruction {
 
   val rs1: Int

diff --git a/src/main/scala/RV32D.scala b/src/main/scala/RV32D.scala
@@ -7,7 +7,7 @@ class FLD( val rs1: Int, val rd: Int ) extends ITypeInstruction( "FLD" ) {
 }
 
 class FSD( val rs1: Int, val rs2: Int ) extends STypeInstruction( "FSD" ) {
-  def apply( cpu: CPU ) = store( cpu, java.lang.Double.doubleToLongBits(cpu.f(rs2)) )
+  def apply( cpu: CPU ) = store( cpu, dtol(cpu.f(rs2)) )
 }
 
 // todo: deal with rm
@@ -18,3 +18,16 @@ class FMADD( val rs1: Int, val rs2: Int, val rd: Int, val rm: Int ) extends R4Ty
       case 1 => cpu.f(rd) = cpu.f(rs1)*cpu.f(rs2) + rs3( cpu )
     }
 }
+
+class FP( val rs1: Int, val rs2: Int, val rd: Int, val mode: Int ) extends FloatRTypeInstruction( Map(0x22 -> "FSGNJ") ) {
+  def apply( cpu: CPU ) =
+    funct( cpu ) match {
+      case 0x22 =>  // FSGNJ
+        mode match {
+          case 0 => ltod( dtol(cpu.f(rs1))&0x7FFFFFFFFFFFFFFFL | dtol(cpu.f(rs2))&0x8000000000000000L )
+          case 1 => ltod( dtol(cpu.f(rs1))&0x7FFFFFFFFFFFFFFFL | dtol(cpu.f(rs2))&0x8000000000000000L^0x8000000000000000L )
+          case 2 => ltod( dtol(cpu.f(rs1))&0x7FFFFFFFFFFFFFFFL ^ (dtol(cpu.f(rs2))&0x8000000000000000L) )
+          case 3 => illegal( cpu )
+        }
+    }
+}
diff --git a/src/main/scala/riscv.scala b/src/main/scala/riscv.scala
@@ -5,6 +5,10 @@ import java.io.ByteArrayOutputStream
 
 package object riscv {
 
+  def dtol( d: Double ) = java.lang.Double.doubleToLongBits( d )
+
+  def ltod( l: Long ) = Long.long2double( l )
+
   def hexByte( a: Int ) = "%02x".format( a&0xFF ).toUpperCase
 
   def hexShort( a: Int ) = hexByte( a>>8 ) + hexByte( a )