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edadma committed Apr 5, 2018
1 parent 1bb09c4 commit 20496f8
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6 changes: 3 additions & 3 deletions README.md
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Expand Up @@ -3,7 +3,7 @@ riscv
[![Build Status](https://www.travis-ci.org/edadma/riscv.svg?branch=master)](https://www.travis-ci.org/edadma/riscv)
[![Coverage Status](https://coveralls.io/repos/github/edadma/riscv/badge.svg?branch=master)](https://coveralls.io/github/edadma/riscv?branch=master)
[![License](https://img.shields.io/badge/license-ISC-blue.svg)](https://opensource.org/licenses/ISC)
[![Version](https://img.shields.io/badge/latest_release-0.1_snapshot_1-orange.svg)](https://www.scala-sbt.org/)
[![Version](https://img.shields.io/badge/latest_release-0.1_snapshot_1.1-orange.svg)](https://www.scala-sbt.org/)

*riscv* is an emulator for the RISC-V ISA (v2.2). Specifically, RV64ID is currently being emulated (with a few missing instructions). Emulation for the compressed instruction sets (RV32C, RV64C) is being worked on. The goal is for RV64GC to be fully supported.

Expand Down Expand Up @@ -80,14 +80,14 @@ Use the following definition to use *riscv* in your Maven project:
<dependency>
<groupId>xyz.hyperreal</groupId>
<artifactId>riscv</artifactId>
<version>0.1_snapshot_1</version>
<version>0.1_snapshot_1.1</version>
</dependency>

Add the following to your `build.sbt` file to use *riscv* in your SBT project:

resolvers += "Hyperreal Repository" at "https://dl.bintray.com/edadma/maven"

libraryDependencies += "xyz.hyperreal" %% "riscv" % "0.1_snapshot_1"
libraryDependencies += "xyz.hyperreal" %% "riscv" % "0.1_snapshot_1.1"


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2 changes: 1 addition & 1 deletion build.sbt
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@@ -1,6 +1,6 @@
name := "riscv"

version := "0.1_snapshot_1"
version := "0.1_snapshot_1.1"

scalaVersion := "2.12.5"

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66 changes: 0 additions & 66 deletions double2str.c

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