fix fld instruction

edadma · Apr 4, 2018 · fef2cf2 · fef2cf2
1 parent f3cbecc
commit fef2cf2
Show file tree

Hide file tree

Showing 6 changed files with 42 additions and 23 deletions.
diff --git a/README.md b/README.md
@@ -1,11 +1,10 @@
+riscv
+=====
 [![Build Status](https://www.travis-ci.org/edadma/riscv.svg?branch=master)](https://www.travis-ci.org/edadma/riscv)
 [![Coverage Status](https://coveralls.io/repos/github/edadma/riscv/badge.svg?branch=master)](https://coveralls.io/github/edadma/riscv?branch=master)
 [![License](https://img.shields.io/badge/license-ISC-blue.svg)](https://opensource.org/licenses/ISC)
 [![Version](https://img.shields.io/badge/latest_release-0.1_snapshot_1-orange.svg)](https://www.scala-sbt.org/)
 
-riscv
-=====
-
 *riscv* is an emulator for the RISC-V ISA (v2.2).  Specifically, RV64ID is currently being emulated (with a few missing instructions).  Emulation for the compressed instruction sets (RV32C, RV64C) is being worked on.  The goal is for RV64GC to be fully supported.
 
 

diff --git a/src/main/scala/CPU.scala b/src/main/scala/CPU.scala
@@ -193,25 +193,27 @@ class CPU( private [riscv] val memory: Memory ) {
       "000 iiiiiiii ddd 00" -> ((operands: Map[Char, Int]) => new C.ADDI4SPN( operands('i'), operands('d') )),
     ) )
 
-  def registers: Unit = {
+  def disassemble: Unit = {
     if (memory.valid( pc )) {
-      val m = memory.find( pc )
-      val low = m.readByte( pc )
-      val (inst, disassembly) =
-        if ((low&3) == 3) {
-          val inst = m.readInt( pc, low )
+    val m = memory.find( pc )
+    val low = m.readByte( pc )
+    val (inst, disassembly) =
+      if ((low&3) == 3) {
+        val inst = m.readInt( pc, low )
 
-          (hexInt( inst ), opcodes32(inst&0x1FFFFFF).disassemble(this))
-        } else {
-          val inst = m.readShort( pc, low )
+        (hexInt( inst ), opcodes32(inst&0x1FFFFFF).disassemble( this ))
+      } else {
+        val inst = m.readShort( pc, low )
 
-          (hexShort( inst ), opcodes16(inst).disassemble(this))
-        }
+        (hexShort( inst ), opcodes16(inst).disassemble( this ))
+      }
 
       printf( "%8x  %s  %s\n", pc, inst, disassembly )
     } else
-      println( s"pc=${pc.toHexString}")
+      println( s"pc=${pc.toHexString}" )
+  }
 
+  def registers: Unit = {
     def regs( start: Int ) {
       for (i <- start until (start + 5 min 32))
         printf( "%21s  ", s"x$i=${x(i).toHexString}" )
@@ -223,6 +225,23 @@ class CPU( private [riscv] val memory: Memory ) {
       regs( i )
   }
 
+  def fregisters: Unit = {
+    def regs( start: Int ) {
+      for (i <- start until (start + 5 min 32))
+        printf( "%21s  ", s"f$i=${"%.2f".format(f(i))}" )
+
+      println
+    }
+
+    for (i <- 0 until 32 by 5)
+      regs( i )
+  }
+
+  def registersAll: Unit = {
+    registers
+    fregisters
+  }
+
   def problem( error: String ) = {
     registers
     sys.error( s"error at ${pc.toHexString}: $error" )

diff --git a/src/main/scala/Main.scala b/src/main/scala/Main.scala
@@ -71,7 +71,10 @@ object Main extends App {
 				mem add new JLineHex( hex(p), reader )
 			} )
 
-		def registers = /*out.println(*/ mach.cpu.registers //)
+		def registers = {
+			mach.cpu.disassemble
+			mach.cpu.registers
+		}
 
 		def dump( start: Int, lines: Int ) = out.println( mach.dump(start, lines) )
 
@@ -132,8 +135,6 @@ object Main extends App {
 //						runAndWait
 					case List( "execute&wait"|"ew" ) =>
 						runAndWait
-					case List( "float"|"f" ) =>
-
 					case List( "help"|"h" ) =>
 						"""
 						|breakpoint (b) <addr>*           set/clear breakpoint at <addr>
@@ -196,7 +197,7 @@ object Main extends App {
 //
 //						registers
 					case List( "registers"|"r" ) =>
-						registersAll
+						mach.cpu.registersAll
 					case List( "reload"|"rl" ) =>
 						interp( reload )
 					case List( "reset"|"re" ) =>

diff --git a/src/main/scala/RV32D.scala b/src/main/scala/RV32D.scala
@@ -3,7 +3,7 @@ package xyz.hyperreal.riscv
 
 
 class FLD( val rs1: Int, val rd: Int ) extends ITypeInstruction( "FLD" ) {
-  def apply( cpu: CPU ) = cpu.f(rd) = load( cpu )
+  def apply( cpu: CPU ) = cpu.f(rd) = ltod( load(cpu) )
 }
 
 class FSD( val rs1: Int, val rs2: Int ) extends STypeInstruction( "FSD" ) {
@@ -19,7 +19,7 @@ class FMADD( val rs1: Int, val rs2: Int, val rd: Int, val rm: Int ) extends R4Ty
     }
 }
 
-class FP( val rs1: Int, val rs2: Int, val rd: Int, val mode: Int ) extends FloatRTypeInstruction( Map(0x22 -> "FSGNJ") ) {
+class FP( val rs1: Int, val rs2: Int, val rd: Int, val mode: Int ) extends FloatRTypeInstruction( Map(0x11 -> "FSGNJ", 1 -> "FADD", 5 -> "FSUB") ) {
   def apply( cpu: CPU ) =
     funct( cpu ) match {
       case 0x11 =>  // FSGNJ

diff --git a/src/main/scala/RV32I.scala b/src/main/scala/RV32I.scala
@@ -199,7 +199,7 @@ class XOR_DIV( val rs1: Int, val rs2: Int, val rd: Int ) extends
 }
 
 class SR_DIVU( val rs1: Int, val rs2: Int, val rd: Int ) extends
-  RTypeInstruction( Map(0 -> "SR", 1 -> "DIVU") ) {
+  RTypeInstruction( Map(0 -> "SRL", 1 -> "DIVU", 0x20 -> "SRA") ) {
   def apply( cpu: CPU ) =
     funct(cpu) match {
       case 0 => cpu(rd) = cpu(rs1) >>> (cpu(rs2)&0x3F)

diff --git a/src/main/scala/riscv.scala b/src/main/scala/riscv.scala
@@ -7,7 +7,7 @@ package object riscv {
 
   def dtol( d: Double ) = java.lang.Double.doubleToLongBits( d )
 
-  def ltod( l: Long ) = Long.long2double( l )
+  def ltod( l: Long ) = java.lang.Double.longBitsToDouble( l )
 
   def hexByte( a: Int ) = "%02x".format( a&0xFF ).toUpperCase