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Added changes for cocotb top testbench for enabling user to add logic to the top level #543

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Added changes for cocotb top testbench for enabling user to add logic to the top level #543

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dbde8a5
remove unwanted driver for openframe in the cocotb top level
M0stafaRady Oct 30, 2023
43b342d
Apply automatic changes to Manifest and README.rst
M0stafaRady Oct 30, 2023
ca4a54f
revert clock to be assigned to anything so iverilog will not remove it
M0stafaRady Oct 30, 2023
3d734b2
Merge branch 'cocotb' of github.com:efabless/caravel into cocotb
M0stafaRady Oct 30, 2023
d161480
Apply automatic changes to Manifest and README.rst
M0stafaRady Oct 30, 2023
6ff76b2
correct the position for sdf annotate in the test so it can be disabl…
M0stafaRady Nov 10, 2023
64677b5
Apply automatic changes to Manifest and README.rst
M0stafaRady Nov 12, 2023
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6 changes: 3 additions & 3 deletions manifest
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ ae07f0d87e69f4dd2026ed841e3a962facac847b verilog/rtl/caravel_openframe.v
d97cb60c8d125d6098111d4f0aa00410515770eb verilog/rtl/caravel_power_routing.v
e54c181033aa019f0edcaed5ffc71e54c3888970 verilog/rtl/chip_io.v
1088531d6a69d82b976d4aca7ae923423680a715 verilog/rtl/chip_io_alt.v
e293e138c6e6f5df76db78bdaa34a35003f6ba5f verilog/rtl/chip_io_openframe.v
b080fd6193e1aee1cd476d8a4c117d65ae1e1178 verilog/rtl/chip_io_openframe.v
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
58fd210a64e502fb231d843eada4052f923d788d verilog/rtl/copyright_block.v
Expand All @@ -47,12 +47,12 @@ c96ba94e5779ea6afe452d89632eaada73e26aab verilog/rtl/mprj_io.v
e0c6ead5e35c1ba01d923c482e953c2af9691524 verilog/rtl/mprj_io_buffer.v
3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v
5287821a0ed1994850a978ef0cd024fac51fb6e8 verilog/rtl/open_source.v
33c8fc54298e5425875aaab8c139074ec7d0e9e9 verilog/rtl/openframe_netlists.v
189532aff9e5e2ebbd99befd05cbf50e948b14af verilog/rtl/openframe_netlists.v
b53c154e6acaf44e858c936c8027d0229608676e verilog/rtl/pads.v
669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
83937790b8f5dbcdd7e9a804b5e9bdf475c0ab7d verilog/rtl/simple_por.v
b9d6114a5067a04dd59cdd46fb988591c16743ce verilog/rtl/spare_logic_block.v
9178c87e3d5196fd3e6abae6fc310e1b663ade0e verilog/rtl/toplevel_cocotb.v
328d6212a394981a4e63a38748b99afaa403a0a0 verilog/rtl/toplevel_cocotb.v
8f0bec01c914efe790a09ffe62bbfe0781069e35 verilog/rtl/xres_buf.v
256190717faa72005cf7656d8443c4c0693b3f78 scripts/set_user_id.py
731116709a44d13225170acc83cd34ff9e00fa39 scripts/generate_fill.py
Expand Down
55 changes: 23 additions & 32 deletions verilog/rtl/toplevel_cocotb.v
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Original file line number Diff line number Diff line change
Expand Up @@ -23,25 +23,7 @@ initial begin
`endif
end
`endif // WAVE_GEN
`ifdef ENABLE_SDF
`ifdef VCS
initial begin
`ifndef CARAVAN
`ifdef ARM
$sdf_annotate({`SDF_PATH,"/",`SDF_POSTFIX,"/swift_caravel.",`CORNER ,".sdf"}, uut,,{`RUN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/caravel_sdf.log"},`ifdef MAX_SDF "MAXIMUM" `else "MINIMUM" `endif );
`else
$sdf_annotate({`SDF_PATH,"/",`SDF_POSTFIX,"/caravel.",`CORNER ,".sdf"}, uut,,{`RUN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/caravel_sdf.log"},`ifdef MAX_SDF "MAXIMUM" `else "MINIMUM" `endif );
`endif //ARM
`else // CARAVAN
$sdf_annotate({`SDF_PATH,"/",`SDF_POSTFIX,"/caravan.", `CORNER,".sdf"}, uut,,{`RUN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/caravan_sdf.log"},`ifdef MAX_SDF "MAXIMUM" `else "MINIMUM" `endif );
`endif

`ifdef USER_SDF_ENABLE
$sdf_annotate({`USER_PROJECT_ROOT,"/signoff/user_project_wrapper/primetime/sdf/",`SDF_POSTFIX,"/user_project_wrapper.", `CORNER,".sdf"}, uut.chip_core.mprj,,{`RUN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/user_prog_sdf.log"},`ifdef MAX_SDF "MAXIMUM" `else "MINIMUM" `endif );
`endif // USER_SDF_ENABLE
end
`endif // VCS
`endif // ENABLE_SDF
wire vddio_tb; // Common 3.3V padframe/ESD power
wire vddio_2_tb; // Common 3.3V padframe/ESD power
wire vssio_tb; // Common padframe/ESD ground
Expand Down Expand Up @@ -153,7 +135,8 @@ caravel uut (
);
`endif // CPU_TYPE_ARM
`else // ! openframe
assign mprj_io_tb[38] = clock_tb;
wire dummy_wire_clk; // iverilog ignores clock_tb if it's not assigned
assign dummy_wire_clk = clock_tb;
caravel_openframe uut (
.vddio (vddio_tb),
.vssio (vssio_tb),
Expand All @@ -173,18 +156,7 @@ caravel uut (
.resetb (resetb_tb)
);

spiflash #(
.FILENAME(FILENAME)
) spiflash (
.csb(mprj_io_tb[39]),
.clk(mprj_io_tb[40]),
.io0(mprj_io_tb[41]),
.io1(mprj_io_tb[42]),
.io2(mprj_io_tb[36]),
.io3(mprj_io_tb[37])
);
// do anything to the unused wires so cocotb can read them when iverilog is used
// apparently iverilog can't read the unused wires and that causes an error in python

assign gpio_tb = 0;
assign vddio_2_tb = 0;
assign vssio_2_tb = 0;
Expand All @@ -196,7 +168,26 @@ caravel uut (
`ifdef USE_USER_VIP
`USER_VIP
`endif // USE_USER_VIP

`ifndef DISABLE_SDF
`ifdef ENABLE_SDF
`ifdef VCS
initial begin
`ifndef CARAVAN
`ifdef ARM
$sdf_annotate({`SDF_PATH,"/",`SDF_POSTFIX,"/swift_caravel.",`CORNER ,".sdf"}, uut,,{`RUN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/caravel_sdf.log"},`ifdef MAX_SDF "MAXIMUM" `else "MINIMUM" `endif );
`else
$sdf_annotate({`SDF_PATH,"/",`SDF_POSTFIX,"/caravel.",`CORNER ,".sdf"}, uut,,{`RUN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/caravel_sdf.log"},`ifdef MAX_SDF "MAXIMUM" `else "MINIMUM" `endif );
`endif //ARM
`else // CARAVAN
$sdf_annotate({`SDF_PATH,"/",`SDF_POSTFIX,"/caravan.", `CORNER,".sdf"}, uut,,{`RUN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/caravan_sdf.log"},`ifdef MAX_SDF "MAXIMUM" `else "MINIMUM" `endif );
`endif
`ifdef USER_SDF_ENABLE
$sdf_annotate({`USER_PROJECT_ROOT,"/signoff/user_project_wrapper/primetime/sdf/",`SDF_POSTFIX,"/user_project_wrapper.", `CORNER,".sdf"}, uut.chip_core.mprj,,{`RUN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/user_prog_sdf.log"},`ifdef MAX_SDF "MAXIMUM" `else "MINIMUM" `endif );
`endif // USER_SDF_ENABLE
end
`endif // VCS
`endif // ENABLE_SDF
`endif // DISABLE_SDF
// make speical variables for the mprj input to assign the input without writing to the output gpios
// cocotb limitation #2587: iverilog deal with array as 1 object not multiple of objects so can't write to only 1 element
wire gpio0;
Expand Down
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