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WARNING: 183 shift/reduce conflicts #179

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shaos opened this issue Dec 29, 2022 · 1 comment
Open

WARNING: 183 shift/reduce conflicts #179

shaos opened this issue Dec 29, 2022 · 1 comment

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@shaos
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shaos commented Dec 29, 2022

My project got this warning after successful MPW Precheck for https://platform.efabless.com/shuttles/MPW-8

STDOUT: {{SUCCESS}} All Checks Passed !!!
STDERR: Generating LALR tables
STDERR: WARNING: 183 shift/reduce conflicts

ID: 5565ebcf-2596-4d3d-8fd5-ca883cce2220
2022-12-28-TestAsyncTrimux 12/28/22 21:42:19 PST 12/28/22 21:46:13 PST succeeded
MPW-Precheck-1.log
@widlarizer
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That's an internal problem of PyVerilog and Verilog itself. I'm certain it will happen no matter the design you throw at the precheck. You can see the same warning in this issue.
This repository could have code to catch and hide this warning though

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@shaos @widlarizer