Sequential entries of a long number with offset for the FPGA microarchitecture on system verilog.
The program uses 4 modules: main, cdd, coder, lower. Below is a table with descriptions of all modules.
| Module | Description |
|---|---|
| main.v | Main module connecting all modules |
| cdd.v | Combinatorial digital device |
| coder.v | Data decoder |
| lower.v | Main module connecting all modules |
The combinatorial digital device module uses 4 states: RESET, WAIT, OUTPUT, READ, SHIFT. Below is a table with descriptions of all states.
| State | Description |
|---|---|
| RESET | Adjust to zero registers and counter |
| WAIT | Waiting to input data |
| OUTPUT | Data output |
| READ | Read data and write to register |
| SHIFT | Shifts registers |
For any problems, comments, or feedback please create an issue here.
This software is released under the MIT License.