Name		Name	Last commit message	Last commit date
parent directory ..
README.md		README.md
add8se_72D.c		add8se_72D.c
add8se_72D.v		add8se_72D.v
add8se_7A2.c		add8se_7A2.c
add8se_7A2.v		add8se_7A2.v
add8se_7J7.c		add8se_7J7.c
add8se_7J7.v		add8se_7J7.v
add8se_7LN.c		add8se_7LN.c
add8se_7LN.v		add8se_7LN.v
add8se_8UN.c		add8se_8UN.c
add8se_8UN.v		add8se_8UN.v
add8se_8XS.c		add8se_8XS.c
add8se_8XS.v		add8se_8XS.v
add8se_8YC.c		add8se_8YC.c
add8se_8YC.v		add8se_8YC.v
add8se_90Z.c		add8se_90Z.c
add8se_90Z.v		add8se_90Z.v
add8se_91D.c		add8se_91D.c
add8se_91D.v		add8se_91D.v
add8se_92J.c		add8se_92J.c
add8se_92J.v		add8se_92J.v
fig.png		fig.png

README.md

Selected circuits

Circuit: 8-bit signed adders (no overflow)
Selection criteria: pareto optimal sub-set wrt. pwr and mae parameters

Parameters of selected circuits

Circuit name	MAE_%	WCE_%	EP_%	MRE_%	MSE	Download
add8se_7A2	0.00	0.00	0.00	0.00	0	[Verilog] [C]
add8se_8YC	0.078	0.39	25.00	0.87	0.2	[Verilog] [C]
add8se_72D	0.27	0.78	62.40	2.88	1.0	[Verilog] [C]
add8se_7LN	0.47	1.17	62.50	4.89	2.8	[Verilog] [C]
add8se_7J7	0.82	2.73	84.38	8.19	7.2	[Verilog] [C]
add8se_91D	1.56	3.52	96.78	15.45	20	[Verilog] [C]
add8se_92J	3.12	6.25	99.22	32.28	77	[Verilog] [C]
add8se_90Z	6.25	12.50	99.80	64.84	313	[Verilog] [C]
add8se_8UN	8.28	26.17	98.49	56.09	672	[Verilog] [C]
add8se_8XS	25.00	50.00	99.95	249.36	4798	[Verilog] [C]

Parameters

References

n/a