Name		Name	Last commit message	Last commit date
parent directory ..
README.md		README.md
fig.png		fig.png
mul8x4u_134.c		mul8x4u_134.c
mul8x4u_134.v		mul8x4u_134.v
mul8x4u_1RU.c		mul8x4u_1RU.c
mul8x4u_1RU.v		mul8x4u_1RU.v
mul8x4u_2UU.c		mul8x4u_2UU.c
mul8x4u_2UU.v		mul8x4u_2UU.v
mul8x4u_30N.c		mul8x4u_30N.c
mul8x4u_30N.v		mul8x4u_30N.v
mul8x4u_3XB.c		mul8x4u_3XB.c
mul8x4u_3XB.v		mul8x4u_3XB.v
mul8x4u_3Y3.c		mul8x4u_3Y3.c
mul8x4u_3Y3.v		mul8x4u_3Y3.v
mul8x4u_485.c		mul8x4u_485.c
mul8x4u_485.v		mul8x4u_485.v
mul8x4u_4ND.c		mul8x4u_4ND.c
mul8x4u_4ND.v		mul8x4u_4ND.v
mul8x4u_4Z7.c		mul8x4u_4Z7.c
mul8x4u_4Z7.v		mul8x4u_4Z7.v
mul8x4u_555.c		mul8x4u_555.c
mul8x4u_555.v		mul8x4u_555.v

README.md

Selected circuits

Circuit: 8x4-bit unsigned multiplier
Selection criteria: pareto optimal sub-set wrt. pwr and mse parameters

Parameters of selected circuits

Circuit name	MAE_%	WCE_%	EP_%	MRE_%	MSE	Download
mul8x4u_2UU	0.00	0.00	0.00	0.00	0	[Verilog] [C]
mul8x4u_3XB	0.012	0.049	37.50	0.33	0.75	[Verilog] [C]
mul8x4u_485	0.039	0.15	60.79	0.90	5.3	[Verilog] [C]
mul8x4u_4ND	0.11	0.44	79.39	2.56	38	[Verilog] [C]
mul8x4u_30N	0.27	1.00	86.43	5.37	209	[Verilog] [C]
mul8x4u_3Y3	0.66	2.17	91.16	10.34	1164	[Verilog] [C]
mul8x4u_1RU	1.71	6.67	92.65	22.99	7822	[Verilog] [C]
mul8x4u_4Z7	3.97	18.63	93.09	39.63	43327	[Verilog] [C]
mul8x4u_134	9.08	34.11	93.33	67.10	230371	[Verilog] [C]
mul8x4u_555	23.35	93.38	93.38	100.00	16831.062e2	[Verilog] [C]

Parameters

References

V. Mrazek, L. Sekanina and Z. Vasicek, "Libraries of Approximate Circuits: Design and Application in CNN Accelerators"