RISCV: 32bit val sign extension

ekaitz-zarraga · Feb 18, 2024 · 589d2ab · 589d2ab
1 parent a986a52
commit 589d2ab
Showing 1 changed file with 13 additions and 1 deletion.
diff --git a/tccgen.c b/tccgen.c
@@ -2383,7 +2383,19 @@ static void gen_cast(CType *type)
                   if (sbt == (VT_LLONG|VT_UNSIGNED))
                     ;
                 else if (sbt & VT_UNSIGNED)
-                    vtop->c.i = (uint32_t)vtop->c.i;
+#if defined(TCC_TARGET_RISCV64)
+                {
+                        /* RISC-V keeps 32bit vals in registers sign-extended.
+                           So here we need a zero-extension.  */
+                        vtop->type.t = VT_LLONG;
+                        vpushi(32);
+                        gen_op(TOK_SHL);
+                        vpushi(32);
+                        gen_op(TOK_SHR);
+                }
+#else
+                    vtop->c.i = (uint32_t)vtop->c.i; // ERROR IS HERE
+#endif
 #if PTR_SIZE == 8
                 else if (sbt == VT_PTR)
                     ;