forked from golang/go
/
parse.go
1238 lines (1177 loc) · 30.4 KB
/
parse.go
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// Copyright 2015 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// Package asm implements the parser and instruction generator for the assembler.
// TODO: Split apart?
package asm
import (
"fmt"
"io"
"log"
"os"
"strconv"
"text/scanner"
"unicode/utf8"
"cmd/asm/internal/arch"
"cmd/asm/internal/flags"
"cmd/asm/internal/lex"
"cmd/internal/obj"
"cmd/internal/obj/x86"
"cmd/internal/src"
"cmd/internal/sys"
)
type Parser struct {
lex lex.TokenReader
lineNum int // Line number in source file.
errorLine int // Line number of last error.
errorCount int // Number of errors.
pc int64 // virtual PC; count of Progs; doesn't advance for GLOBL or DATA.
input []lex.Token
inputPos int
pendingLabels []string // Labels to attach to next instruction.
labels map[string]*obj.Prog
toPatch []Patch
addr []obj.Addr
arch *arch.Arch
ctxt *obj.Link
firstProg *obj.Prog
lastProg *obj.Prog
dataAddr map[string]int64 // Most recent address for DATA for this symbol.
isJump bool // Instruction being assembled is a jump.
errorWriter io.Writer
}
type Patch struct {
prog *obj.Prog
label string
}
func NewParser(ctxt *obj.Link, ar *arch.Arch, lexer lex.TokenReader) *Parser {
return &Parser{
ctxt: ctxt,
arch: ar,
lex: lexer,
labels: make(map[string]*obj.Prog),
dataAddr: make(map[string]int64),
errorWriter: os.Stderr,
}
}
// panicOnError is enabled when testing to abort execution on the first error
// and turn it into a recoverable panic.
var panicOnError bool
func (p *Parser) errorf(format string, args ...interface{}) {
if panicOnError {
panic(fmt.Errorf(format, args...))
}
if p.lineNum == p.errorLine {
// Only one error per line.
return
}
p.errorLine = p.lineNum
if p.lex != nil {
// Put file and line information on head of message.
format = "%s:%d: " + format + "\n"
args = append([]interface{}{p.lex.File(), p.lineNum}, args...)
}
fmt.Fprintf(p.errorWriter, format, args...)
p.errorCount++
if p.errorCount > 10 && !*flags.AllErrors {
log.Fatal("too many errors")
}
}
func (p *Parser) pos() src.XPos {
return p.ctxt.PosTable.XPos(src.MakePos(p.lex.Base(), uint(p.lineNum), 0))
}
func (p *Parser) Parse() (*obj.Prog, bool) {
for p.line() {
}
if p.errorCount > 0 {
return nil, false
}
p.patch()
return p.firstProg, true
}
// WORD [ arg {, arg} ] (';' | '\n')
func (p *Parser) line() bool {
// Skip newlines.
var tok lex.ScanToken
for {
tok = p.lex.Next()
// We save the line number here so error messages from this instruction
// are labeled with this line. Otherwise we complain after we've absorbed
// the terminating newline and the line numbers are off by one in errors.
p.lineNum = p.lex.Line()
switch tok {
case '\n', ';':
continue
case scanner.EOF:
return false
}
break
}
// First item must be an identifier.
if tok != scanner.Ident {
p.errorf("expected identifier, found %q", p.lex.Text())
return false // Might as well stop now.
}
word := p.lex.Text()
var cond string
operands := make([][]lex.Token, 0, 3)
// Zero or more comma-separated operands, one per loop.
nesting := 0
colon := -1
for tok != '\n' && tok != ';' {
// Process one operand.
items := make([]lex.Token, 0, 3)
for {
tok = p.lex.Next()
if len(operands) == 0 && len(items) == 0 {
if p.arch.InFamily(sys.ARM, sys.ARM64, sys.AMD64, sys.I386) && tok == '.' {
// Suffixes: ARM conditionals or x86 modifiers.
tok = p.lex.Next()
str := p.lex.Text()
if tok != scanner.Ident {
p.errorf("instruction suffix expected identifier, found %s", str)
}
cond = cond + "." + str
continue
}
if tok == ':' {
// Labels.
p.pendingLabels = append(p.pendingLabels, word)
return true
}
}
if tok == scanner.EOF {
p.errorf("unexpected EOF")
return false
}
// Split operands on comma. Also, the old syntax on x86 for a "register pair"
// was AX:DX, for which the new syntax is DX, AX. Note the reordering.
if tok == '\n' || tok == ';' || (nesting == 0 && (tok == ',' || tok == ':')) {
if tok == ':' {
// Remember this location so we can swap the operands below.
if colon >= 0 {
p.errorf("invalid ':' in operand")
return true
}
colon = len(operands)
}
break
}
if tok == '(' || tok == '[' {
nesting++
}
if tok == ')' || tok == ']' {
nesting--
}
items = append(items, lex.Make(tok, p.lex.Text()))
}
if len(items) > 0 {
operands = append(operands, items)
if colon >= 0 && len(operands) == colon+2 {
// AX:DX becomes DX, AX.
operands[colon], operands[colon+1] = operands[colon+1], operands[colon]
colon = -1
}
} else if len(operands) > 0 || tok == ',' || colon >= 0 {
// Had a separator with nothing after.
p.errorf("missing operand")
}
}
if p.pseudo(word, operands) {
return true
}
i, present := p.arch.Instructions[word]
if present {
p.instruction(i, word, cond, operands)
return true
}
p.errorf("unrecognized instruction %q", word)
return true
}
func (p *Parser) instruction(op obj.As, word, cond string, operands [][]lex.Token) {
p.addr = p.addr[0:0]
p.isJump = p.arch.IsJump(word)
for _, op := range operands {
addr := p.address(op)
if !p.isJump && addr.Reg < 0 { // Jumps refer to PC, a pseudo.
p.errorf("illegal use of pseudo-register in %s", word)
}
p.addr = append(p.addr, addr)
}
if p.isJump {
p.asmJump(op, cond, p.addr)
return
}
p.asmInstruction(op, cond, p.addr)
}
func (p *Parser) pseudo(word string, operands [][]lex.Token) bool {
switch word {
case "DATA":
p.asmData(operands)
case "FUNCDATA":
p.asmFuncData(operands)
case "GLOBL":
p.asmGlobl(operands)
case "PCDATA":
p.asmPCData(operands)
case "TEXT":
p.asmText(operands)
default:
return false
}
return true
}
func (p *Parser) start(operand []lex.Token) {
p.input = operand
p.inputPos = 0
}
// address parses the operand into a link address structure.
func (p *Parser) address(operand []lex.Token) obj.Addr {
p.start(operand)
addr := obj.Addr{}
p.operand(&addr)
return addr
}
// parseScale converts a decimal string into a valid scale factor.
func (p *Parser) parseScale(s string) int8 {
switch s {
case "1", "2", "4", "8":
return int8(s[0] - '0')
}
p.errorf("bad scale: %s", s)
return 0
}
// operand parses a general operand and stores the result in *a.
func (p *Parser) operand(a *obj.Addr) {
//fmt.Printf("Operand: %v\n", p.input)
if len(p.input) == 0 {
p.errorf("empty operand: cannot happen")
return
}
// General address (with a few exceptions) looks like
// $sym±offset(SB)(reg)(index*scale)
// Exceptions are:
//
// R1
// offset
// $offset
// Every piece is optional, so we scan left to right and what
// we discover tells us where we are.
// Prefix: $.
var prefix rune
switch tok := p.peek(); tok {
case '$', '*':
prefix = rune(tok)
p.next()
}
// Symbol: sym±offset(SB)
tok := p.next()
name := tok.String()
if tok.ScanToken == scanner.Ident && !p.atStartOfRegister(name) {
// We have a symbol. Parse $sym±offset(symkind)
p.symbolReference(a, name, prefix)
// fmt.Printf("SYM %s\n", obj.Dconv(&emptyProg, 0, a))
if p.peek() == scanner.EOF {
return
}
}
// Special register list syntax for arm: [R1,R3-R7]
if tok.ScanToken == '[' {
if prefix != 0 {
p.errorf("illegal use of register list")
}
p.registerList(a)
p.expectOperandEnd()
return
}
// Register: R1
if tok.ScanToken == scanner.Ident && p.atStartOfRegister(name) {
if p.atRegisterShift() {
// ARM shifted register such as R1<<R2 or R1>>2.
a.Type = obj.TYPE_SHIFT
a.Offset = p.registerShift(tok.String(), prefix)
if p.peek() == '(' {
// Can only be a literal register here.
p.next()
tok := p.next()
name := tok.String()
if !p.atStartOfRegister(name) {
p.errorf("expected register; found %s", name)
}
a.Reg, _ = p.registerReference(name)
p.get(')')
}
} else if p.atRegisterExtension() {
a.Type = obj.TYPE_REG
p.registerExtension(a, tok.String(), prefix)
p.expectOperandEnd()
return
} else if r1, r2, scale, ok := p.register(tok.String(), prefix); ok {
if scale != 0 {
p.errorf("expected simple register reference")
}
a.Type = obj.TYPE_REG
a.Reg = r1
if r2 != 0 {
// Form is R1:R2. It is on RHS and the second register
// needs to go into the LHS.
panic("cannot happen (Addr.Reg2)")
}
}
// fmt.Printf("REG %s\n", obj.Dconv(&emptyProg, 0, a))
p.expectOperandEnd()
return
}
// Constant.
haveConstant := false
switch tok.ScanToken {
case scanner.Int, scanner.Float, scanner.String, scanner.Char, '+', '-', '~':
haveConstant = true
case '(':
// Could be parenthesized expression or (R). Must be something, though.
tok := p.next()
if tok.ScanToken == scanner.EOF {
p.errorf("missing right parenthesis")
return
}
rname := tok.String()
p.back()
haveConstant = !p.atStartOfRegister(rname)
if !haveConstant {
p.back() // Put back the '('.
}
}
if haveConstant {
p.back()
if p.have(scanner.Float) {
if prefix != '$' {
p.errorf("floating-point constant must be an immediate")
}
a.Type = obj.TYPE_FCONST
a.Val = p.floatExpr()
// fmt.Printf("FCONST %s\n", obj.Dconv(&emptyProg, 0, a))
p.expectOperandEnd()
return
}
if p.have(scanner.String) {
if prefix != '$' {
p.errorf("string constant must be an immediate")
return
}
str, err := strconv.Unquote(p.get(scanner.String).String())
if err != nil {
p.errorf("string parse error: %s", err)
}
a.Type = obj.TYPE_SCONST
a.Val = str
// fmt.Printf("SCONST %s\n", obj.Dconv(&emptyProg, 0, a))
p.expectOperandEnd()
return
}
a.Offset = int64(p.expr())
if p.peek() != '(' {
switch prefix {
case '$':
a.Type = obj.TYPE_CONST
case '*':
a.Type = obj.TYPE_INDIR // Can appear but is illegal, will be rejected by the linker.
default:
a.Type = obj.TYPE_MEM
}
// fmt.Printf("CONST %d %s\n", a.Offset, obj.Dconv(&emptyProg, 0, a))
p.expectOperandEnd()
return
}
// fmt.Printf("offset %d \n", a.Offset)
}
// Register indirection: (reg) or (index*scale). We are on the opening paren.
p.registerIndirect(a, prefix)
// fmt.Printf("DONE %s\n", p.arch.Dconv(&emptyProg, 0, a))
p.expectOperandEnd()
return
}
// atStartOfRegister reports whether the parser is at the start of a register definition.
func (p *Parser) atStartOfRegister(name string) bool {
// Simple register: R10.
_, present := p.arch.Register[name]
if present {
return true
}
// Parenthesized register: R(10).
return p.arch.RegisterPrefix[name] && p.peek() == '('
}
// atRegisterShift reports whether we are at the start of an ARM shifted register.
// We have consumed the register or R prefix.
func (p *Parser) atRegisterShift() bool {
// ARM only.
if !p.arch.InFamily(sys.ARM, sys.ARM64) {
return false
}
// R1<<...
if lex.IsRegisterShift(p.peek()) {
return true
}
// R(1)<<... Ugly check. TODO: Rethink how we handle ARM register shifts to be
// less special.
if p.peek() != '(' || len(p.input)-p.inputPos < 4 {
return false
}
return p.at('(', scanner.Int, ')') && lex.IsRegisterShift(p.input[p.inputPos+3].ScanToken)
}
// atRegisterExtension reports whether we are at the start of an ARM64 extended register.
// We have consumed the register or R prefix.
func (p *Parser) atRegisterExtension() bool {
// ARM64 only.
if p.arch.Family != sys.ARM64 {
return false
}
// R1.xxx
if p.peek() == '.' {
return true
}
return false
}
// registerReference parses a register given either the name, R10, or a parenthesized form, SPR(10).
func (p *Parser) registerReference(name string) (int16, bool) {
r, present := p.arch.Register[name]
if present {
return r, true
}
if !p.arch.RegisterPrefix[name] {
p.errorf("expected register; found %s", name)
return 0, false
}
p.get('(')
tok := p.get(scanner.Int)
num, err := strconv.ParseInt(tok.String(), 10, 16)
p.get(')')
if err != nil {
p.errorf("parsing register list: %s", err)
return 0, false
}
r, ok := p.arch.RegisterNumber(name, int16(num))
if !ok {
p.errorf("illegal register %s(%d)", name, r)
return 0, false
}
return r, true
}
// register parses a full register reference where there is no symbol present (as in 4(R0) or R(10) but not sym(SB))
// including forms involving multiple registers such as R1:R2.
func (p *Parser) register(name string, prefix rune) (r1, r2 int16, scale int8, ok bool) {
// R1 or R(1) R1:R2 R1,R2 R1+R2, or R1*scale.
r1, ok = p.registerReference(name)
if !ok {
return
}
if prefix != 0 && prefix != '*' { // *AX is OK.
p.errorf("prefix %c not allowed for register: %c%s", prefix, prefix, name)
}
c := p.peek()
if c == ':' || c == ',' || c == '+' {
// 2nd register; syntax (R1+R2) etc. No two architectures agree.
// Check the architectures match the syntax.
switch p.next().ScanToken {
case ',':
if !p.arch.InFamily(sys.ARM, sys.ARM64) {
p.errorf("(register,register) not supported on this architecture")
return
}
case '+':
if p.arch.Family != sys.PPC64 {
p.errorf("(register+register) not supported on this architecture")
return
}
}
name := p.next().String()
r2, ok = p.registerReference(name)
if !ok {
return
}
}
if p.peek() == '*' {
// Scale
p.next()
scale = p.parseScale(p.next().String())
}
return r1, r2, scale, true
}
// registerShift parses an ARM/ARM64 shifted register reference and returns the encoded representation.
// There is known to be a register (current token) and a shift operator (peeked token).
func (p *Parser) registerShift(name string, prefix rune) int64 {
if prefix != 0 {
p.errorf("prefix %c not allowed for shifted register: $%s", prefix, name)
}
// R1 op R2 or r1 op constant.
// op is:
// "<<" == 0
// ">>" == 1
// "->" == 2
// "@>" == 3
r1, ok := p.registerReference(name)
if !ok {
return 0
}
var op int16
switch p.next().ScanToken {
case lex.LSH:
op = 0
case lex.RSH:
op = 1
case lex.ARR:
op = 2
case lex.ROT:
// following instructions on ARM64 support rotate right
// AND, ANDS, TST, BIC, BICS, EON, EOR, ORR, MVN, ORN
op = 3
}
tok := p.next()
str := tok.String()
var count int16
switch tok.ScanToken {
case scanner.Ident:
if p.arch.Family == sys.ARM64 {
p.errorf("rhs of shift must be integer: %s", str)
} else {
r2, ok := p.registerReference(str)
if !ok {
p.errorf("rhs of shift must be register or integer: %s", str)
}
count = (r2&15)<<8 | 1<<4
}
case scanner.Int, '(':
p.back()
x := int64(p.expr())
if p.arch.Family == sys.ARM64 {
if x >= 64 {
p.errorf("register shift count too large: %s", str)
}
count = int16((x & 63) << 10)
} else {
if x >= 32 {
p.errorf("register shift count too large: %s", str)
}
count = int16((x & 31) << 7)
}
default:
p.errorf("unexpected %s in register shift", tok.String())
}
if p.arch.Family == sys.ARM64 {
return int64(r1&31)<<16 | int64(op)<<22 | int64(uint16(count))
} else {
return int64((r1 & 15) | op<<5 | count)
}
}
// registerExtension parses a register with extension or arrangement.
// There is known to be a register (current token) and an extension operator (peeked token).
func (p *Parser) registerExtension(a *obj.Addr, name string, prefix rune) {
if prefix != 0 {
p.errorf("prefix %c not allowed for shifted register: $%s", prefix, name)
}
reg, ok := p.registerReference(name)
if !ok {
p.errorf("unexpected %s in register extension", name)
return
}
isIndex := false
num := int16(0)
isAmount := true // Amount is zero by default
ext := ""
if p.peek() == lex.LSH {
// (Rn)(Rm<<2), the shifted offset register.
ext = "LSL"
} else {
// (Rn)(Rm.UXTW<1), the extended offset register.
// Rm.UXTW<<3, the extended register.
p.get('.')
tok := p.next()
ext = tok.String()
}
if p.peek() == lex.LSH {
// parses left shift amount applied after extension: <<Amount
p.get(lex.LSH)
tok := p.get(scanner.Int)
amount, err := strconv.ParseInt(tok.String(), 10, 16)
if err != nil {
p.errorf("parsing left shift amount: %s", err)
}
num = int16(amount)
} else if p.peek() == '[' {
// parses an element: [Index]
p.get('[')
tok := p.get(scanner.Int)
index, err := strconv.ParseInt(tok.String(), 10, 16)
p.get(']')
if err != nil {
p.errorf("parsing element index: %s", err)
}
isIndex = true
isAmount = false
num = int16(index)
}
switch p.arch.Family {
case sys.ARM64:
err := arch.ARM64RegisterExtension(a, ext, reg, num, isAmount, isIndex)
if err != nil {
p.errorf(err.Error())
}
default:
p.errorf("register extension not supported on this architecture")
}
}
// symbolReference parses a symbol that is known not to be a register.
func (p *Parser) symbolReference(a *obj.Addr, name string, prefix rune) {
// Identifier is a name.
switch prefix {
case 0:
a.Type = obj.TYPE_MEM
case '$':
a.Type = obj.TYPE_ADDR
case '*':
a.Type = obj.TYPE_INDIR
}
// Weirdness with statics: Might now have "<>".
isStatic := false
if p.peek() == '<' {
isStatic = true
p.next()
p.get('>')
}
if p.peek() == '+' || p.peek() == '-' {
a.Offset = int64(p.expr())
}
if isStatic {
a.Sym = p.ctxt.LookupStatic(name)
} else {
a.Sym = p.ctxt.Lookup(name)
}
if p.peek() == scanner.EOF {
if prefix == 0 && p.isJump {
// Symbols without prefix or suffix are jump labels.
return
}
p.errorf("illegal or missing addressing mode for symbol %s", name)
return
}
// Expect (SB), (FP), (PC), or (SP)
p.get('(')
reg := p.get(scanner.Ident).String()
p.get(')')
p.setPseudoRegister(a, reg, isStatic, prefix)
}
// setPseudoRegister sets the NAME field of addr for a pseudo-register reference such as (SB).
func (p *Parser) setPseudoRegister(addr *obj.Addr, reg string, isStatic bool, prefix rune) {
if addr.Reg != 0 {
p.errorf("internal error: reg %s already set in pseudo", reg)
}
switch reg {
case "FP":
addr.Name = obj.NAME_PARAM
case "PC":
if prefix != 0 {
p.errorf("illegal addressing mode for PC")
}
addr.Type = obj.TYPE_BRANCH // We set the type and leave NAME untouched. See asmJump.
case "SB":
addr.Name = obj.NAME_EXTERN
if isStatic {
addr.Name = obj.NAME_STATIC
}
case "SP":
addr.Name = obj.NAME_AUTO // The pseudo-stack.
default:
p.errorf("expected pseudo-register; found %s", reg)
}
if prefix == '$' {
addr.Type = obj.TYPE_ADDR
}
}
// registerIndirect parses the general form of a register indirection.
// It is can be (R1), (R2*scale), (R1)(R2*scale), (R1)(R2.SXTX<<3) or (R1)(R2<<3)
// where R1 may be a simple register or register pair R:R or (R, R) or (R+R).
// Or it might be a pseudo-indirection like (FP).
// We are sitting on the opening parenthesis.
func (p *Parser) registerIndirect(a *obj.Addr, prefix rune) {
p.get('(')
tok := p.next()
name := tok.String()
r1, r2, scale, ok := p.register(name, 0)
if !ok {
p.errorf("indirect through non-register %s", tok)
}
p.get(')')
a.Type = obj.TYPE_MEM
if r1 < 0 {
// Pseudo-register reference.
if r2 != 0 {
p.errorf("cannot use pseudo-register in pair")
return
}
// For SB, SP, and FP, there must be a name here. 0(FP) is not legal.
if name != "PC" && a.Name == obj.NAME_NONE {
p.errorf("cannot reference %s without a symbol", name)
}
p.setPseudoRegister(a, name, false, prefix)
return
}
a.Reg = r1
if r2 != 0 {
// TODO: Consistency in the encoding would be nice here.
if p.arch.InFamily(sys.ARM, sys.ARM64) {
// Special form
// ARM: destination register pair (R1, R2).
// ARM64: register pair (R1, R2) for LDP/STP.
if prefix != 0 || scale != 0 {
p.errorf("illegal address mode for register pair")
return
}
a.Type = obj.TYPE_REGREG
a.Offset = int64(r2)
// Nothing may follow
return
}
if p.arch.Family == sys.PPC64 {
// Special form for PPC64: (R1+R2); alias for (R1)(R2*1).
if prefix != 0 || scale != 0 {
p.errorf("illegal address mode for register+register")
return
}
a.Type = obj.TYPE_MEM
a.Scale = 1
a.Index = r2
// Nothing may follow.
return
}
}
if r2 != 0 {
p.errorf("indirect through register pair")
}
if prefix == '$' {
a.Type = obj.TYPE_ADDR
}
if r1 == arch.RPC && prefix != 0 {
p.errorf("illegal addressing mode for PC")
}
if scale == 0 && p.peek() == '(' {
// General form (R)(R*scale).
p.next()
tok := p.next()
if p.atRegisterExtension() {
p.registerExtension(a, tok.String(), prefix)
} else if p.atRegisterShift() {
// (R1)(R2<<3)
p.registerExtension(a, tok.String(), prefix)
} else {
r1, r2, scale, ok = p.register(tok.String(), 0)
if !ok {
p.errorf("indirect through non-register %s", tok)
}
if r2 != 0 {
p.errorf("unimplemented two-register form")
}
a.Index = r1
if scale == 0 && p.arch.Family == sys.ARM64 {
// scale is 1 by default for ARM64
a.Scale = 1
} else {
a.Scale = int16(scale)
}
}
p.get(')')
} else if scale != 0 {
// First (R) was missing, all we have is (R*scale).
a.Reg = 0
a.Index = r1
a.Scale = int16(scale)
}
}
// registerList parses an ARM or ARM64 register list expression, a list of
// registers in []. There may be comma-separated ranges or individual
// registers, as in [R1,R3-R5] or [V1.S4, V2.S4, V3.S4, V4.S4].
// For ARM, only R0 through R15 may appear.
// For ARM64, V0 through V31 with arrangement may appear.
//
// For 386/AMD64 register list specifies 4VNNIW-style multi-source operand.
// For range of 4 elements, Intel manual uses "+3" notation, for example:
// VP4DPWSSDS zmm1{k1}{z}, zmm2+3, m128
// Given asm line:
// VP4DPWSSDS Z5, [Z10-Z13], (AX)
// zmm2 is Z10, and Z13 is the only valid value for it (Z10+3).
// Only simple ranges are accepted, like [Z0-Z3].
//
// The opening bracket has been consumed.
func (p *Parser) registerList(a *obj.Addr) {
if p.arch.InFamily(sys.I386, sys.AMD64) {
p.registerListX86(a)
} else {
p.registerListARM(a)
}
}
func (p *Parser) registerListARM(a *obj.Addr) {
// One range per loop.
var maxReg int
var bits uint16
var arrangement int64
switch p.arch.Family {
case sys.ARM:
maxReg = 16
case sys.ARM64:
maxReg = 32
default:
p.errorf("unexpected register list")
}
firstReg := -1
nextReg := -1
regCnt := 0
ListLoop:
for {
tok := p.next()
switch tok.ScanToken {
case ']':
break ListLoop
case scanner.EOF:
p.errorf("missing ']' in register list")
return
}
switch p.arch.Family {
case sys.ARM64:
// Vn.T
name := tok.String()
r, ok := p.registerReference(name)
if !ok {
p.errorf("invalid register: %s", name)
}
reg := r - p.arch.Register["V0"]
p.get('.')
tok := p.next()
ext := tok.String()
curArrangement, err := arch.ARM64RegisterArrangement(reg, name, ext)
if err != nil {
p.errorf(err.Error())
}
if firstReg == -1 {
// only record the first register and arrangement
firstReg = int(reg)
nextReg = firstReg
arrangement = curArrangement
} else if curArrangement != arrangement {
p.errorf("inconsistent arrangement in ARM64 register list")
} else if nextReg != int(reg) {
p.errorf("incontiguous register in ARM64 register list: %s", name)
}
regCnt++
nextReg = (nextReg + 1) % 32
case sys.ARM:
// Parse the upper and lower bounds.
lo := p.registerNumber(tok.String())
hi := lo
if p.peek() == '-' {
p.next()
hi = p.registerNumber(p.next().String())
}
if hi < lo {
lo, hi = hi, lo
}
// Check there are no duplicates in the register list.
for i := 0; lo <= hi && i < maxReg; i++ {
if bits&(1<<lo) != 0 {
p.errorf("register R%d already in list", lo)
}
bits |= 1 << lo
lo++
}
default:
p.errorf("unexpected register list")
}
if p.peek() != ']' {
p.get(',')
}
}
a.Type = obj.TYPE_REGLIST
switch p.arch.Family {
case sys.ARM:
a.Offset = int64(bits)
case sys.ARM64:
offset, err := arch.ARM64RegisterListOffset(firstReg, regCnt, arrangement)
if err != nil {
p.errorf(err.Error())
}
a.Offset = offset
default:
p.errorf("register list not supported on this architecuture")
}
}
func (p *Parser) registerListX86(a *obj.Addr) {
// Accept only [RegA-RegB] syntax.
// Don't use p.get() to provide better error messages.
loName := p.next().String()
lo, ok := p.arch.Register[loName]
if !ok {
if loName == "EOF" {
p.errorf("register list: expected ']', found EOF")
} else {
p.errorf("register list: bad low register in `[%s`", loName)
}
return
}
if tok := p.next().ScanToken; tok != '-' {
p.errorf("register list: expected '-' after `[%s`, found %s", loName, tok)
return
}
hiName := p.next().String()
hi, ok := p.arch.Register[hiName]
if !ok {
p.errorf("register list: bad high register in `[%s-%s`", loName, hiName)
return
}
if tok := p.next().ScanToken; tok != ']' {
p.errorf("register list: expected ']' after `[%s-%s`, found %s", loName, hiName, tok)
}
a.Type = obj.TYPE_REGLIST
a.Reg = lo
a.Offset = x86.EncodeRegisterRange(lo, hi)
}
// register number is ARM-specific. It returns the number of the specified register.
func (p *Parser) registerNumber(name string) uint16 {
if p.arch.Family == sys.ARM && name == "g" {
return 10
}
if name[0] != 'R' {
p.errorf("expected g or R0 through R15; found %s", name)
return 0
}
r, ok := p.registerReference(name)
if !ok {
return 0
}
reg := r - p.arch.Register["R0"]
if reg < 0 {
// Could happen for an architecture having other registers prefixed by R
p.errorf("expected g or R0 through R15; found %s", name)
return 0
}
return uint16(reg)
}
// Note: There are two changes in the expression handling here
// compared to the old yacc/C implementations. Neither has