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Update ld
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elpekenin committed Jul 27, 2023
1 parent f4f6519 commit 579e150
Showing 1 changed file with 71 additions and 20 deletions.
@@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio

Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
Expand All @@ -15,10 +15,15 @@
*/

/*
* STM32H750xB memory setup.
* ST32F750xB generic setup.
*
* SPI flash ( 8mb) at 0x60000000
* embedded flash (128kb) at 0x08000000
* AXI SRAM - BSS, Data, Heap.
* SRAM1+SRAM2 - None.
* SRAM3 - NOCACHE, ETH.
* SRAM4 - None.
* DTCM-RAM - Main Stack, Process Stack.
* ITCM-RAM - None.
* BCKP SRAM - None.
*/
MEMORY
{
Expand All @@ -30,14 +35,14 @@ MEMORY
flash5 : org = 0x00000000, len = 0
flash6 : org = 0x00000000, len = 0
flash7 : org = 0x00000000, len = 0
ram0 : org = 0x20000000, len = 64k
ram1 : org = 0x00000000, len = 0
ram2 : org = 0x00000000, len = 0
ram3 : org = 0x00000000, len = 0
ram4 : org = 0x00000000, len = 0
ram5 : org = 0x00000000, len = 0
ram6 : org = 0x00000000, len = 0
ram7 : org = 0x00000000, len = 0
ram0 : org = 0x24000000, len = 512K
ram1 : org = 0x30000000, len = 128K
ram2 : org = 0x30020000, len = 128K
ram3 : org = 0x30040000, len = 32K
ram4 : org = 0x38000000, len = 64k /* AHB SRAM4 */
ram5 : org = 0x20000000, len = 64k /* DTCM-RAM */
ram6 : org = 0x00000000, len = 64k /* ITCM-RAM */
ram7 : org = 0x38800000, len = 4k /* BCKP SRAM */
}

/* For each data/text section two region are defined, a virtual region
Expand Down Expand Up @@ -68,24 +73,70 @@ REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);

/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
REGION_ALIAS("MAIN_STACK_RAM", ram5);

/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
REGION_ALIAS("PROCESS_STACK_RAM", ram5);

/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM", ram5);
REGION_ALIAS("DATA_RAM_LMA", flash0);

/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
REGION_ALIAS("BSS_RAM", ram5);

/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
REGION_ALIAS("HEAP_RAM", ram5);

/* Stack rules inclusion.*/
INCLUDE rules_stacks.ld

/*===========================================================================*/
/* Custom sections for STM32H7xx. */
/* SRAM3 is assumed to be marked non-cacheable using MPU. */
/*===========================================================================*/

/* RAM region to be used for nocache segment.*/
REGION_ALIAS("NOCACHE_RAM", ram3);

/* RAM region to be used for eth segment.*/
REGION_ALIAS("ETH_RAM", ram3);

SECTIONS
{
/* Special section for non cache-able areas.*/
.nocache (NOLOAD) : ALIGN(4)
{
__nocache_base__ = .;
*(.nocache)
*(.nocache.*)
*(.bss.__nocache_*)
. = ALIGN(4);
__nocache_end__ = .;
} > NOCACHE_RAM

/* Special section for Ethernet DMA non cache-able areas.*/
.eth (NOLOAD) : ALIGN(4)
{
__eth_base__ = .;
*(.eth)
*(.eth.*)
*(.bss.__eth_*)
. = ALIGN(4);
__eth_end__ = .;
} > ETH_RAM
}

/* Code rules inclusion.*/
INCLUDE rules_code.ld

/* Data rules inclusion.*/
INCLUDE rules_data.ld

/* Memory rules inclusion.*/
INCLUDE rules_memory.ld

/* Generic rules inclusion.*/
INCLUDE rules.ld

/* TinyUF2 bootloader reset support */
_board_dfu_dbl_tap = ORIGIN(ram0) + 64k; /* this is based off the linker file for tinyuf2 */
_board_dfu_dbl_tap = ORIGIN(ram5) + 64k; /* this is based off the linker file for tinyuf2 */

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